Patent application number | Description | Published |
20120154224 | HANDHELD DEVICE AND PLANAR ANTENNA THEREOF - A handheld device and a planar antenna thereof are provided. The planar antenna comprises a radiator having a feeding point, a first short point and a second short point. The feeding point is coupled to a circuit board of the handheld device so that the handheld device transmits and receives a RF (radio frequency) signal through the radiator. The first short point is coupled to a ground of the circuit board so as to be grounded. A control element is disposed on the handheld device or the planar antenna in order to control the second short point to be selectively electrically coupled to the ground so that the planar antenna can operate at two different central frequencies. Furthermore, the planar antenna can operate at multiple central frequencies by changing a position of the second short point contacted to the radiator. | 06-21-2012 |
20120229346 | HANDHELD DEVICE - A handheld device is provided, wherein the handheld device comprises a housing, a circuit board, a planar antenna and a switch. The housing comprising an outer surface is configured to define a receiving space. The circuit board is disposed in the receiving space. The planar antenna comprises a metal layer, wherein the metal layer comprising a first connecting point and a second connecting point is patterned on the outer surface. The switch comprising a first electrode and a second electrode is configured to control the electrical connection between the first connecting point and the second connecting point, wherein the first electrode and the second electrode are electrically connected between the first connecting point and the second connecting point. The planar antenna operates at a first central band when the switch is turned on, and operates at a second central band when the switch is turned off. | 09-13-2012 |
20120287014 | HANDHELD DEVICE AND PLANAR ANTENNA THEREOF - A handheld device and a planar antenna thereof are provided. The planar antenna comprises a radiator, a screening element and a switch. The screening element is configured to make the planar antenna operating in a first high-frequency (HF) current path and a first low-frequency (LF) current path, and the switch is configured to make the planar antenna operating in a second HF current path and a second LF current path. The planar antenna operates at a first HF central frequency corresponding to the first HF current path and a first LF central frequency corresponding to the first LF current path when the switch is turned off, and operates at a second HF central frequency corresponding to the second HF current path and a second LF central frequency corresponding to the second LF current path when the switch is turned on. | 11-15-2012 |
20130099996 | HANDHELD DEVICE AND PLANAR ANTENNA THEREOF - A handheld device and a planar antenna thereof are provided. The planar antenna comprises a radiator with an open terminal, a short terminal, a first feeding terminal and a second feeding terminal. The short terminal is coupled to a ground terminal. The first feeding terminal is formed between the open terminal and the short terminal, and coupled to a radio frequency (RF) signal terminal. The second feeding terminal is formed between the open terminal and the first feeding terminal, and coupled to the first feeding terminal by a transmission line and a switch element. The radiator resonates at the first central frequency when the switch element is turned off, and resonates at the second central frequency when the switch element is turned on. | 04-25-2013 |
20140080548 | Handheld Communication Device and Communication Method of the Same - A communication method used in a handheld communication device is provided. The communication method comprises the steps outlined below. Whether a voice communication is established is determined. When the voice communication is established, a sensing element is activated to determine whether the handheld communication device is operated in a hand mode. When the handheld communication device is not operated in the hand mode, an antenna module of the handheld communication device would be operated in a first operation frequency band to perform the voice communication. When the handheld communication device is operated in the hand mode, the antenna module of the handheld communication device would be operated in a second operation frequency band to perform the voice communication, in which the second operation frequency band is higher than the first operation frequency band. A handheld communication device is disclosed herein as well. | 03-20-2014 |
20150022404 | HANDHELD DEVICE - A handheld device is provided, wherein the handheld device comprises a housing, a circuit board, a planar antenna and a switch. The housing comprising an outer surface is configured to define a receiving space. The circuit board is disposed in the receiving space. The planar antenna comprises a metal layer, wherein the metal layer comprising a first connecting point and a second connecting point is patterned on the outer surface. The switch comprising a first electrode and a second electrode is configured to control the electrical connection between the first connecting point and the second connecting point, wherein the first electrode and the second electrode are electrically connected between the first connecting point and the second connecting point. The planar antenna operates at a first central band when the switch is turned on, and operates at a second central band when the switch is turned off. | 01-22-2015 |
20150077298 | MOBILE DEVICE AND ANTENNA STRUCTURE USING IONIC POLYMER METAL COMPOSITE THEREIN - A mobile device includes an antenna structure, a signal source, and an IPMC (Ionic Polymer Metal Composite). The signal source is configured to excite the antenna structure. The IPMC is configured as a flexible actuator to adjust a resonant length of the antenna structure in such a manner that the antenna structure is capable of operating in multiple bands. | 03-19-2015 |
Patent application number | Description | Published |
20130026614 | STRUCTURE AND METHOD FOR BUMP TO LANDING TRACE RATIO - The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. | 01-31-2013 |
20130026619 | BUMP STRUCTURES - The embodiments of bump and bump-on-trace (BOT) structures provide bumps with recess regions for reflowed solder to fill. The recess regions are placed in areas of the bumps where reflow solder is most likely to protrude. The recess regions reduce the risk of bump to trace shorting. As a result, yield can be improved. | 01-31-2013 |
20130032923 | Integrated Inductor - A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization. | 02-07-2013 |
20130256874 | Elongated Bumps in Integrated Circuit Devices - A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 μm. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer. | 10-03-2013 |
20140077365 | Metal Bump and Method of Manufacturing Same - An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width. | 03-20-2014 |
20140110847 | BUMP-ON-TRACE INTERCONNECTION STRUCTURE FOR FLIP-CHIP PACKAGES - A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width W | 04-24-2014 |
20140131865 | Structure and Method for Bump to Landing Trace Ratio - The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. | 05-15-2014 |
20140167253 | Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices - Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width. | 06-19-2014 |
20140291838 | Design Scheme for Connector Site Spacing and Resulting Structures - A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. | 10-02-2014 |
20140346673 | Methods and Apparatus for bump-on-trace Chip Packaging - Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill. | 11-27-2014 |
20150084186 | BUMP STRUCTURE HAVING A SINGLE SIDE RECESS - A bump structure includes a first end, and a second end opposite the first end. The bump structure further includes a first side connected between the first end and the second end. The bump structure further includes a second side opposite the first side. The second side is connected between the first end and the second end, and the second side comprises a recess for a reflowed solder material to fill. | 03-26-2015 |
20150187719 | Trace Design for Bump-on-Trace (BOT) Assembly - A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small. | 07-02-2015 |
Patent application number | Description | Published |
20130316506 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers. | 11-28-2013 |
20140175527 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure. | 06-26-2014 |
20140273368 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer. | 09-18-2014 |
20150091059 | PROCESS FOR FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR (FinFET) STRUCTURE AND PRODUCT THEREOF - A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fm together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer. | 04-02-2015 |
20150093870 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE STRUCTURE - A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer. | 04-02-2015 |
20150255563 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING MULTI-LAYER HARD MASK - A method for manufacturing a semiconductor device is provided, comprising steps of providing a substrate with an underlying layer formed thereon; forming a gate layer overlying the underlying layer; and forming a multi-layer hard mask layer on the gate layer, and the multi-layer hard mask layer comprising a plurality of material layers and a top hard mask formed on the material layers, wherein the gate layer and the top hard mask contain the same element, such as silicon. | 09-10-2015 |
Patent application number | Description | Published |
20130194076 | Process Monitoring System and Related Method - A process monitoring system comprises a radio frequency identification (RFID) tag disposed on a position corresponding to the component for receiving a radio-frequency (RF) signal and responding a corresponding feedback signal during a stage of the manufacturing process, an RFID reader transmitting the RF signal and receiving the feedback signal during the stage of the manufacturing process, and a determination module coupled to the RFID reader for determining a duration of the stage according to reception of the feedback signal. | 08-01-2013 |
20130341409 | Multi-Function Radio-Frequency Device, Computer System and Method of Operating Multi-Function Radio-Frequency Device - A multi-function Radio-Frequency device integrated into a computer system is disclosed and includes a substrate including a first surface and a second surface opposite to each other, a touchpad area disposed on the first surface of the substrate for generating a touch signal according to a touch situation, an antenna disposed on the first surface and/or the second surface of the substrate for receiving and transmitting a Radio-Frequency signal, and a control module disposed on the second surface of the substrate and coupled to the touchpad area and the antenna for generating a touch control signal according to the touch signal and generating an identification signal according to the Radio-Frequency signal to the computer system. | 12-26-2013 |
20140292489 | POSITIONING SYSTEM AND POSITIONING METHOD - A positioning system includes an object storage device, a plurality of RFID (Radio Frequency Identification) tags, an antenna, and an RFID reader. The object storage device includes a plurality of storage vacancies. The RFID tags are respectively disposed in the storage vacancies. The antenna is disposed in the object storage device. The RFID reader detects the RFID tags via the antenna. The RFID reader stores a corresponding relationship between the RFID tags and the storage vacancies. When an object is placed in a specific storage vacancy, the RFID reader determines that a specific RFID tag disposed in the specific storage vacancy is no longer detectable, and determines that the specific storage vacancy is occupied further according to the corresponding relationship. | 10-02-2014 |