Patent application number | Description | Published |
20090033530 | METHOD OF CONTROLLING PIPELINE ANALOG-TO-DIGITAL CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER IMPLEMENTING THE SAME - Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC. | 02-05-2009 |
20090086072 | DUAL CDS/PxGA CIRCUIT - Provided is a dual sampling/pixel gain amplifier (CDS/PxGA) circuit with a shared amplifier, and more particularly, to a dual CDS/PxGA circuit for adjusting a gain of an amplifier based on capacitance. The dual CDS/PxGA circuit comprises: a first sampler for sampling a reset level and a data level of a first pixel; a second sampler for sampling a reset level and a data level of a second pixel; and an operational amplifier for receiving sampling values from the first and second samplers, calculating output signals of the first and second pixels using the sampling values, and amplifying the calculated output signals. Thus, it is possible to reduce a speed of an operational amplifier by using the dual CDS/PxGA structure, reduce power consumption by sharing the operational amplifier, and obtain a variable gain of a wide range by adjusting capacitance using a capacitor array. | 04-02-2009 |
20090091383 | GAIN AMPLIFIER HAVING SWITCHED-CAPACITOR STRUCTURE FOR MINIMIZING SETTLING TIME - Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized. | 04-09-2009 |
20090091387 | SWITCHED-CAPACITOR VARIABLE GAIN AMPLIFIER HAVING HIGH VOLTAGE GAIN LINEARITY - Provided is a switched-capacitor variable gain amplifier having high voltage gain linearity. According to the above amplifier, a sampling capacitor is shared and used at a sampling phase and an amplification phase, and thus a voltage gain error caused by capacitor mismatch can be reduced. Also, using a unit capacitor array enables circuit design and layout to be simplified. Further, in the amplifier, a voltage gain can be easily controlled to be more or less than 1, as necessary, and power consumption and kT/C noise can be reduced by a feedback factor that is relatively large, so that gain amplification performance can be improved. | 04-09-2009 |
20100019321 | MULTIPLE-GATE MOS TRANSISTOR USING Si SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region. | 01-28-2010 |
20100052643 | BAND-GAP REFERENCE VOLTAGE GENERATOR - A band-gap reference voltage generator is provided. N-channel metal oxide semiconductor (NMOS) transistors are respectively connected to bipolar transistors in parallel. A Complementary To Absolute Temperature (CTAT) voltage that is inversely proportional to absolute temperature is reduced by a threshold voltage of the NMOS transistor. A weight for a temperature coefficient of a Proportional To Absolute Temperature (PTAT) voltage that is directly proportional to absolute temperature is reduced and a resistance ratio for a temperature coefficient of 0 is reduced by about | 03-04-2010 |
20100066583 | MULTI-STAGE SUCCESSIVE APPROXIMATION REGISTER ANALOG-TODIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTING METHOD USING THE SAME - A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC. | 03-18-2010 |
20100085229 | ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER - Provided is an algorithmic analog-to-digital converter (ADC). In the algorithmic ADC, the number of preprocessing amplifiers used in a flash ADC is reduced by sharing the preprocessing amplifiers in the flash ADC, and thus chip size can be reduced. In addition, power consumption can be reduced by dynamically decreasing the bandwidth of an operational amplifier included in a multiplying digital-to-analog converter (MDAC) according to a required resolution. | 04-08-2010 |
20100123611 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-DIGITAL CONVERTER AND METHOD OF DRIVING THE SAME - A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved. | 05-20-2010 |
20100156469 | HIGH-SPEED MULTI-STAGE VOLTAGE COMPARATOR - A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC). | 06-24-2010 |
20100156692 | MULTI-STAGE DUAL SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTOR AND METHOD OF PERFORMING ANALOG-TO-DIGITAL CONVERSION USING THE SAME - A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier. | 06-24-2010 |
20110018605 | OFFSET-VOLTAGE CALIBRATION CIRCUIT - Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage. | 01-27-2011 |
20110018629 | REFERENCE VOLTAGE SUPPLY CIRCUIT - A reference voltage supply circuit is provided. The reference voltage supply circuit includes a first amplifier for amplifying a first input voltage and a fed back first reference voltage, a second amplifier for amplifying a second input voltage and a fed back second reference voltage, a reference voltage generator for generating the first reference voltage and the second reference voltage according to output signals of the first and second amplifiers and feeding the first and second reference voltages back to the first and second amplifiers, and a glitch remover turned on/off according to an input pulse signal to conduct or cut off current flowing between a power supply terminal and the ground. | 01-27-2011 |
20110032134 | DIGITAL-TO-ANALOG CONVERTER - A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized. Consequently, it is possible to minimize heat noise and device mismatching. | 02-10-2011 |
20110102220 | PIPELINE ANALOG-TO-DIGITAL CONVERTER - Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced. | 05-05-2011 |
20110227774 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-DIGITAL CONVERTER AND METHOD FOR OPERATING THE SAME - A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2 | 09-22-2011 |
20120062406 | ANALOG DIGITAL CONVERTING DEVICE - Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal. | 03-15-2012 |
20120146820 | PIPELINED ANALOG DIGITAL CONVERTOR - Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to measure and correct a pipelined conversion stage gain error and an offset error due to a finite voltage gain operational amplifier and capacitor mismatch. The pipelined analog-to-digital converter includes a pipelined conversion stage error measuring and correcting circuit measuring and correcting an error generated from an conversion stage, so that an error of a conversion stage is minimized and a chip realization area and power consumption are reduced. | 06-14-2012 |
20120146821 | PIPELINED ANALOG DIGITAL CONVERTOR - Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to improve the complexity of a logic circuit for dividing a correction period and a no-correction period of a digital output. The pipelined analog-to-digital converter performs a logic correction operation via binary shifting at data error correction. Accordingly, although the resolution increases, it is possible to reduce the complexity and area of a logic circuit. | 06-14-2012 |
20120146830 | ANALOG DIGITAL CONVERTER - Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array. | 06-14-2012 |
20120242266 | SENSORLESS BLDC MOTOR SYSTEMS AND DRIVING METHODS OF SENSORLESS BLDC MOTOR - Provided is a sensorless BLDC motor system. The sensorless BLDC motor system includes a BLDC motor, a comparator, a motor controller, a three-phase inverter, and a mode selector. The BLDC motor includes first to third coils. The comparator compares a voltage of a specific coil of the first to third coils with a neutral-point voltage to output the compared result. The voltage of the specific coil becomes equal to the neutral-point voltage and a specific time elapses, and then the motor controller generates first and second coil control signals based on the compared result. The three-phase inverter supplies a source voltage or ground voltage to the specific coil, or floats the specific coil, in response to the first and second coil control signals. The mode selector selects a driving mode of the BLDC motor by adjusting the specific time. | 09-27-2012 |
20120268052 | MOTOR CONTROL DEVICE AND METHOD OF CONTROLLING THE SAME - A motor control device including a preprocessing portion calculating a counter electromotive force using an analog operation is provided. The motor control device may include an offset compensation portion and a counter electromotive force measuring portion. The offset compensation portion receives a three-phase current signal from the motor and compensates an offset of the three-phase current signal. The counter electromotive force measuring portion receives the compensated current signal and a three-phase voltage signal from the motor and calculates the received current signal and the received voltage signal using an analog operation to provide the calculated result. | 10-25-2012 |
20130027094 | TRIANGULAR WAVE GENERATOR AND METHOD GENERATING TRIANGULAR WAVE THEREOF - Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope. | 01-31-2013 |
20130076552 | ANALOG-DIGITAL CONVERTER AND POWER SAVING METHOD THEREOF - Disclosed is an analog-digital converter which includes a pre-amplifier configured to output a comparison result between a sampled analog input signal and a reference signal and to control a power supply operation in response to a power control signal; a digital signal processor configured to generate a digital signal based on the comparison result; a power controller configured to generate an amplifier operation clock signal for controlling the pre-amplifier; and a counter configured to count the number of falling edges of the amplifier operation clock signal and to detect a power interruption point of time of the pre-amplifier according to the counted falling edge number. The power controller generates the power control signal for interrupting a power to be supplied to the pre-amplifier when the power interruption point of time of the pre-amplifier is detected. | 03-28-2013 |
20130135126 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND OPERATION METHOD THEREOF - Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier. | 05-30-2013 |
20140002285 | APPARATUS AND METHOD FOR CALIBRATING TIME CONSTANT, AND LOW PASS DELTA SIGMA MODULATION APPARATUS INCLUDING THE SAME | 01-02-2014 |
20140022102 | APPARATUS AND METHOD FOR CALIBRATING OFFSET VOLTAGE AND CONTINUOUS TIME DELTA-SIGMA MODULATION APPARATUS INCLUDING THE SAME - When an enable signal representing an offset calibration mode is received, a continuous time delta-sigma modulation apparatus generates a first signal using first and second pulse signals representing outputs of the continuous time delta-sigma modulation apparatus and an operation frequency of the continuous time delta-sigma modulation apparatus, generates first and second output bits by performing a counting operation according to a counting method that is determined according to a pulse signal of first and second comparators, applies a voltage corresponding to the first output bit to a body of a first transistor of a primary integrator, and applies a voltage corresponding to the second output bit to a body of a second transistor of the primary integrator. | 01-23-2014 |
20140064355 | DELTA-SIGMA MODULATOR AND TRANSMITTER INCLUDING THE SAME - A delta-sigma modulator and a transmitter apparatus including the same are disclosed. The delta-sigma modulator includes a first integrator, a second integrator, a first comparator configured to compare an output signal of the second integrator and a reference signal, and output a first comparison signal, a second comparator configured to compare the output signal of the second integrator and the reference signal, and output a second comparison signal, a first DAC configured to output the first signal corresponding to the first comparison signal and the second comparison signal, a second DAC configured to output the second signal corresponding to the first comparison signal and the second comparison signal, a delayer configured to generate a delayed signal that delays the first comparison signal and the second comparison signal by a predetermined time, and an output DAC configured to generate an output signal having a multi-level corresponding to the delayed signal. | 03-06-2014 |
20140159700 | BANDGAP REFERENCE VOLTAGE GENERATOR - Disclosed is a bandgap reference voltage generator insensitive to changes of process, voltage, and temperature. A bandgap reference voltage generator may detect current having characteristic of CTAT and current having characteristic of PTAT which flow in a current compensation part included in an amplification part, and provide body voltage to one of two input transistors included in the amplification part in response to ratio of the two currents when the ratio is different from the preconfigured reference value. Thus, characteristics according to changes of parameters of elements and change of offset of the amplification part due to changes of PVT may be enhanced, and a characteristic of power supply rejection ratio (PSRR) may be enhanced. | 06-12-2014 |
20150017932 | SIGNAL AMPLIFICATION APPARATUS AND METHOD - A signal amplification apparatus includes a first modulator configured to receive an envelope signal, use a predetermined reference level to separate the received envelope signal into a first period and a second period, digitally modulate a signal of the second period to output the digitally modulated signal to a first output terminal, and output a signal of the first period to a second output terminal. Further, the signal amplification apparatus includes a second modulator configured to mix the digital modulated signal input through the first output terminal with a phase modulated carrier signal; an envelope modulator configured to output the signal of the first period as a power supply signal; and a power amplifier configured to amplify the mixed signal output by the second modulator to output the amplified signal. | 01-15-2015 |
20150078500 | METHOD OF CORRECTING TIME MISALIGNMENT BETWEEN ENVELOPE AND PHASE COMPONENTS - Provided is a method of correcting a time misalignment between envelope and phase components in a transmitting apparatus which separates envelope and phase components of a signal, processes them, and then recombines them to transmit the recombined signal. For this, in a method of correcting a time misalignment between envelope and phase components according to an embodiment of the present invention, a time misalignment is corrected by applying a time delay to at least one of envelope and phase components in digital and analog signal processing operations, or applying a time delay to an envelope or phase component by a pre-processing operation. | 03-19-2015 |