Patent application number | Description | Published |
20080297238 | CURRENT SOURCE CIRCUIT - A current source circuit is provided. The circuit includes a first transistor and at least one second transistor. A first source/drain terminal of the first transistor is coupled to a bias voltage. A second source/drain terminal of the first transistor is used to receive a current signal, and the second source/drain terminal of the first transistor is coupled to a gate terminal of the first transistor. A first source/drain terminal of the second transistor is grounded. A second source/drain terminal of the second transistor is coupled to a voltage source and outputs a bias current. A gate terminal of the second transistor is coupled to the gate terminal of the first transistor. | 12-04-2008 |
20090015974 | ESD DETECTION CIRCUIT - An ESD detection circuit which includes: a triggering circuit for generating an ESD trigger signal when the ESD detection circuit is in ESD mode; a bias circuit for providing at least a first bias voltage and a second bias voltage for controlling the operation of the triggering circuit; a trigger controlling circuit for decreasing a voltage difference between the first bias voltage and the second bias voltage when the ESD detection circuit is in the ESD mode, and for controlling a duration of the ESD trigger signal that is generated by the triggering circuit; and an activating control circuit for activating the trigger controlling circuit and the triggering circuit to enter the ESD mode according to a voltage level at a first node. | 01-15-2009 |
20090179222 | SILICON CONTROLLED RECTIFIER - A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive type well and the second conductive type doped region is located within the first conductive type well and shaped as a polygonal ring concentric to the first conductive type well. | 07-16-2009 |
20090296293 | ESD PROTECTION CIRCUIT FOR DIFFERENTIAL I/O PAIR - An ESD protection circuit for a differential I/O pair is provided. The circuit includes an ESD detection circuit, a discharge device, and four diodes. The first diode is coupled between the first I/O pin and the discharge device in a forward direction toward the discharge device. The second diode is coupled between the second I/O pin and the discharge device in a forward direction toward the second I/O pin. The third diode is coupled between the discharge device and the positive power line in a forward direction toward the positive power line. The fourth diode is coupled between the discharge device and the negative power line in a forward direction toward the discharge device. Via an output end, the ESD detection circuit triggers the discharge device during ESD events. | 12-03-2009 |
20100118454 | ESD PROTECTION CIRCUITRY WITH MULTI-FINGER SCRS - Self-triggered Multi-finger SCRs used in ESD protection circuitry capable of turning on all SCR fingers of the multi-finger SCRs include a first source, a second source, N SCR units, (N−1) diodes, and N resistors. Each of the N SCR units includes a first node, a second node coupled to the second source, and a trigger node. An nth diode of the (N−1) diodes is coupled between a first node of an nth SCR unit and a trigger node of an (n+1)th SCR unit. An nth resistor is coupled between the first node of the nth SCR unit and the first source, wherein n and N are integers. The (N−1) diodes can be replaced by directly coupled the first node of the nth SCR unit to the trigger node of the (n+1)th SCR unit when a trigger pulse is applied at the trigger node of a first SCR unit. | 05-13-2010 |
20100140659 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND RELATED CIRCUIT - An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N | 06-10-2010 |
20110043953 | ESD PROTECTION CIRCUIT WITH MERGED TRIGGERING MECHANISM - An ESD protection circuit has a merged triggering mechanism. The ESD protection circuit comprises: an ESD detection circuit, for detecting an ESD voltage to generate a control signal; a first type ESD protection device, for outputting a first trigger current; a second type ESD protection device, for receiving a second trigger current; and a trigger circuit, for constituting a conductive path according to the control signal, such that the trigger circuit can receive the first trigger current from the first type ESD protection device and outputs the second trigger current to the second type ESD protection device. | 02-24-2011 |
20110149449 | HIGH-VOLTAGE-TOLERANT ESD CLAMP CIRCUIT WITH LOW LEAKAGE CURRENT FABRICATED BY LOW-VOLTAGE CMOS PROCESS - An electrostatic discharge (ESD) clamp circuit is provided, which includes a plurality of identical module circuits. The anode of the first module circuit is coupled to the cathode of the ESD clamp circuit. The anode of each of the other module circuits is coupled to the cathode of the previous module circuit. The cathode of the last module circuit is coupled to the ground terminal of the ESD clamp circuit. Each module circuit includes a conduction path and a detection circuit. The detection circuit is coupled to the anode, the cathode and the conduction path of the module circuit. When the rising speed of the voltage at the anode of the module circuit surpasses a threshold value, the detection circuit makes the conduction path conducting. | 06-23-2011 |
20110198678 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event. | 08-18-2011 |
20110255200 | ELECTROSTATIC DISCHARGE CIRCUIT FOR INTEGRATED CIRCUIT WITH MULTIPLE POWER DOMAIN - An ESD protection circuit with multiple domains, which comprises: an ESD protection device, coupled between a first power supplying line and a first ground line; a first internal circuit, having a first terminal coupled to the first power supplying line; a first switch, coupled between a second terminal of the first internal circuit and a second ground line; and a first ESD detection circuit, coupled to the first switch, for detecting an ESD signal, and controls the first switch to be non-conductive when the ESD signal occurs. | 10-20-2011 |
20120044605 | ESD PROTECTION FOR HIGH-VOLTAGE-TOLERANCE OPEN-DRAIN OUTPUT PAD - A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor. | 02-23-2012 |
20120146151 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region. | 06-14-2012 |
20120290046 | LOAD-ADAPTIVE BIOELECTRIC CURRENT STIMULATOR - The disclosure relates to a load-adaptive bioelectrical current stimulator, which comprises a current output module, an adaptation module and a control module. The current output module generates a stimulus current to an electrode. The adaptation module detects the electrical status of the stimulus current passing through the electrode and generates a feedback signal to the control module. According to the feedback signal, the control module controls the current output module to stabilize the output status of the stimulus current adaptively. Thereby, the load-adaptive bioelectrical current stimulator can use the feedback control mechanism to regulate the value of the stimulus current to adapt to variation of load impedance. | 11-15-2012 |
20130044397 | ESD PROTECTION CIRCUIT - ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate. | 02-21-2013 |
20130088801 | ELECTROSTATIC DISCHARGE PROTECTION APPARATUS - An electrostatic discharge (ESD) protection apparatus includes at least one first transistor and at least one second transistor. The first transistor includes a control terminal, a first terminal, a second terminal, and a bulk. The control terminal and the second terminal of the first transistor are coupled to each other. The first terminal of the first transistor is coupled to one of a pad and a power rail line. Likewise, the second transistor also includes a control terminal, a first terminal, and a second terminal. The first terminal of the second transistor is coupled to the bulk of the first transistor, the bulk of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the other of the pad and the power rail line. | 04-11-2013 |
20130094113 | INITIAL-ON SCR DEVICE FOR ON-CHIP ESD PROTECTION - A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor. | 04-18-2013 |
20130172958 | CURRENT STIMULATOR - The disclosure relates to a current stimulator, which comprises a high voltage output module, a voltage control module and a charge pump module. The high voltage output module includes a plurality of stacked transistors, and receives an input control signal able to turn on/off the current stimulator and a first voltage. A second voltage is generated by adding the voltages output by all the transistors to the first voltage and then output to the voltage control module. The voltage control module outputs a voltage control signal able to stabilize the stimulus current for the load according to the second voltage and the load impedance variation. The charge pump regulates the first voltage according to the voltage control signal, and outputs the regulated first voltage to the high voltage output module. Thereby, the current stimulator can adaptively stabilize the stimulus current, responding to load impedance variation. | 07-04-2013 |
20130221834 | PLANAR MIRCO-TUBE DISCHARGER STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability. | 08-29-2013 |
20130314826 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event. | 11-28-2013 |
20140063663 | POWER-RAIL ELECTRO-STATIC DISCHARGE (ESD) CLAMP CIRCUIT - A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation. | 03-06-2014 |
Patent application number | Description | Published |
20100253392 | I/O BUFFER WITH TWICE THE SUPPLY VOLTAGE TOLERANCE USING NORMAL SUPPLY VOLTAGE DEVICES - The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems. | 10-07-2010 |
20110291742 | OUTPUT BUFFER WITH PROCESS AND TEMPERATURE COMPENSATION - An output buffer with process and temperature compensation comprises an enable terminal, a clock generator, a PMOS threshold voltage detector, an NMOS threshold voltage detector, a first comparator, a second comparator, a first compensation code generator, a second compensation code generator and an output buffer stage, wherein the output buffer stage has an output stage, the output buffer stage means for controlling a drive current generated by the output stage, wherein the output stage has a first voltage output terminal, and the modulated drive current is capable of compensating slew rate of the first voltage output terminal. | 12-01-2011 |
20110298498 | CORNER DETECTOR - A corner detector comprises a PMOS threshold voltage detector and an NMOS threshold voltage detector, the PMOS threshold voltage detector is composed of a first clock terminal, a first CMOS inverter, a first capacitor, a PMOS threshold voltage function generator and a first voltage output terminal, wherein the PMOS threshold voltage function generator is electrically connected to the first capacitor and applied to generate a first formula of voltage signal as a function of threshold voltage, the NMOS threshold voltage detector is composed of a second clock terminal, a second CMOS inverter, a second capacitor, an NMOS threshold voltage function generator and a second voltage output terminal, wherein the NMOS threshold voltage function generator is electrically connected to the second capacitor and applied to generate a second formula of voltage signal as a function of threshold voltage. | 12-08-2011 |
20130057992 | ESD PROTECTION CIRCUIT - An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor. | 03-07-2013 |
Patent application number | Description | Published |
20090213508 | ESD protection for high-voltage-tolerance open-drain output pad - A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor. | 08-27-2009 |
20100253418 | CHARGE PUMP CIRCUITS, SYSTEMS, AND OPERATIONAL METHODS THEREOF - A charge pump circuit includes at least one stage between an input end and an output end. The at least one stage includes a first CMOS transistor coupled with a first capacitor and a second CMOS transistor coupled with a second capacitor. The at least one stage is capable of receiving a first timing signal and a second timing signal for pumping an input voltage at the input end to an output voltage at the output end. During a transitional period of the first timing signal and the second timing signal, the at least one stage is capable of substantially turning off at least one of the first CMOS transistor and the second CMOS transistor for substantially reducing leakage currents flowing through at least one of the first CMOS transistor and the second CMOS transistor. | 10-07-2010 |
20120099228 | ESD PROTECTION FOR RF CIRCUITS - An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, includes an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node and a LC-tank structure coupled between the VDD power rail node and the VSS power rail node and to the RF I/O pad. The LC-tank structure includes a first ESD block between the VDD power rail node and the RF I/O pad, and a second ESD block between the VSS power rail node and the RF I/O pad. At least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes. | 04-26-2012 |
20120169409 | CHARGE PUMP CIRCUITS, SYSTEMS, AND OPERATIONAL METHODS THEREOF - A charge pump circuit includes at least one stage between an input end and an output end. The at least one stage includes a first CMOS transistor coupled with a first capacitor and a second CMOS transistor coupled with a second capacitor. The at least one stage is capable of receiving a first timing signal and a second timing signal for pumping an input voltage at the input end to an output voltage at the output end. During a transitional period of the first timing signal and the second timing signal, the at least one stage is capable of substantially turning off at least one of the first CMOS transistor and the second CMOS transistor for substantially reducing leakage currents flowing through at least one of the first CMOS transistor and the second CMOS transistor. | 07-05-2012 |
20120170161 | ELECTROSTATIC DISCHARGE CIRCUIT FOR RADIO FREQUENCY TRANSMITTERS - A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier; an ESD detection circuit that triggers the SCR responsive to detect an electrostatic discharge on an ESD bus; and an ESD clamp circuit that is coupled to the first voltage line. | 07-05-2012 |
20130163127 | ESD PROTECTION CIRCUIT - An electrostatic discharge protection circuit includes an input node coupled to receive an input signal and an output node coupled to output the input signal to an internal circuit. A first inductor is coupled to the input node and to the output node, and a second inductor is coupled to the output node and to a first power supply node through a resistance. A plurality of protection devices are coupled to the first and second inductors and are disposed in parallel with each other. | 06-27-2013 |
Patent application number | Description | Published |
20090021872 | ESD protection circuit with active triggering - An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor. | 01-22-2009 |
20090096432 | Loading reduction device and method - An active loading-reduction device is provided for a circuit. The circuit has functional circuitry coupled to a terminal to receive an alternating voltage. The circuit also has an electrostatic discharge protector that is coupled to the terminal. The active loading-reduction device includes active circuitry that is adapted to be coupled to a power supply to provide a reactance to counteract a reactance provided by the electrostatic discharge protector at the terminal of the circuit. | 04-16-2009 |
20090135533 | Power-rail ESD protection circuit with ultra low gate leakage - An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented. | 05-28-2009 |
20090287435 | SYSTEM-LEVEL ESD DETECTION CIRCUIT - An ESD detection circuit for detecting a level of an ESD voltage on a power rail is provided. The ESD detection circuit includes a resistive component, a diode unit, and a controller. The resistive component is coupled between a detection node and a ground node corresponding to the power rail. The diode unit is coupled between the power rail and the detection node in a forward direction toward the power rail. The controller, coupled to the detection node, is used for determining the level of the ESD voltage based on the voltage of the detection node and the breakdown voltage of the diode unit. | 11-19-2009 |
20090296295 | Power-rail ESD protection circuit with ultra low gate leakage - An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the negative power line and an input terminal of the triggering unit. The MOS capacitor is coupled between the positive power line and an input terminal of the triggering unit for ESD protection. During a normal power operation, a switching terminal of the triggering unit enables the MOS capacitor to be coupled between the negative power line and an input terminal of the triggering unit. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented. | 12-03-2009 |
20100142107 | ESD protection circuit with active triggering - An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor. | 06-10-2010 |
20100148797 | ESD DETECTION CIRCUIT AND RELATED METHOD THEREOF - An electro-static discharge (ESD) detection circuit is provided. The ESD detection circuit includes: a first power pad for receiving a first supply voltage; a second power pad for receiving a second supply voltage; an RC circuit having an impedance component coupled between the first power pad and a first terminal and having an capacitive component coupled between the first terminal and a second terminal, wherein the second terminal is not directly connected to the second supply voltage; a trigger circuit couples to the first power pad, the second power pad, and the RC circuit, for generating an ESD trigger signal according to a voltage level at the first terminal and a voltage level at the second terminal, and a bias circuit coupled between the first power pad and the second power pad for providing a bias voltage to the second terminal. | 06-17-2010 |
Patent application number | Description | Published |
20090032837 | ASYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER - The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier. | 02-05-2009 |
20090032838 | SYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER - The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas. | 02-05-2009 |
20090236631 | Bidirectional PNPN silicon-controlled rectifier - The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semiconductor area are coupled to a cathode, and wherein the fourth semiconductor area is of second conduction type, and the fifth semiconductor area is of first conduction type. | 09-24-2009 |
20090273006 | Bidirectional silicon-controlled rectifier - The present invention discloses a bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from the bird's beak effect of a field oxide layer, which results in crystalline defects, a concentrated current and a higher magnetic field and then causes abnormal operation of a rectifier. Thereby, the present invention can also reduce signal loss. | 11-05-2009 |
20140106064 | METHOD FOR FABRICATING A PLANAR MICRO-TUBE DISCHARGER STRUCTURE - A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block., and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability. | 04-17-2014 |