Patent application number | Description | Published |
20080209741 | Blade structure of an electric hair trimmer - A blade structure of an electric hair trimmer is a blade set, comprising a fixed blade, a movable blade and a vibration seat which is driven by a motor. A front end of both fixed and movable blades is provided with a plurality of teeth to cut the hair by an alternate movement. The lower sections of edge parts at two sides of a tooth of the movable blade are extended outward from top to bottom to form with externally expanded surfaces with sharp transection angles. Accordingly, when hair is cut, a contact area of the edge parts between the hair is decreased, to largely reduce resistance to cutting, such that the hair can be cut off well with improved speed and efficiency and can be prevented from being damaged. Besides, lifetime of usage of blade structure in the electric hair trimmer can be extended. | 09-04-2008 |
20110302789 | Hair Trimmer - A hair trimmer includes a fixture having an upper and a lower tie plates, with an elastic element between the upper and lower tie plates; at least two cutting units at an end of the upper and lower tie plates, with each cutting unit having a corresponding cutting part, and an end of each cutting part having notches of different depths; and at least two combing units assembled with the upper and lower tie plates and corresponding to an exterior side of each cutting unit, with each combing unit including a teeth part which corresponds to each other and is parallel to the cutting part, and an end of each teeth part having comb slots of different depths. Therefore, a multiedged thinning can be carried out while trimming and it allows the hair to have more different levels of edge and a sense of beauty. | 12-15-2011 |
Patent application number | Description | Published |
20130069242 | ARRANGEMENT OF THROUGH-SUBSTRATE VIAS FOR STRESS RELIEF AND IMPROVED DENSITY - A semiconductor device structure for a three-dimensional integrated circuit has a semiconductor substrate having a plurality of through-substrate vias provided in the substrate, wherein three or more of the plurality of through-substrate vias are arranged in a hexagonal packing array with respect to their design-rule circle. | 03-21-2013 |
20130239070 | RC EXTRACTION FOR SINGLE PATTERNING SPACER TECHNIQUE - A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns. | 09-12-2013 |
20140019930 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout. | 01-16-2014 |
20140137062 | PATTERN MATCHING BASED PARASITIC EXTRACTION WITH PATTERN REUSE - The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs. Moreover, the extraction result may be applied multiple times for a given design simultaneously, speeding up computation time. The extraction result may also be applied to a plurality of designs simultaneously. | 05-15-2014 |
20140282289 | CELL BOUNDARIES FOR SELF ALIGNED MULTIPLE PATTERNING ABUTMENTS - A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern. | 09-18-2014 |
20140282293 | EDA TOOL AND METHOD FOR CONFLICT DETECTION DURING MULTI-PATTERNING LITHOGRAPHY - A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing. | 09-18-2014 |
20140282337 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT - A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also comprises extracting, using the RC extraction tool, at least one second parasitic capacitance among electrical components outside the regions of the plurality of regions. The method further comprises combining, using a netlist generator tool, the extracted first and second parasitic capacitances into a netlist representing the layout. The RC extraction tool is configured to extract the first parasitic capacitances inside at least one region of the plurality of regions using a methodology more accurate than that for extracting the second parasitic capacitances. | 09-18-2014 |
20140298284 | STANDARD CELL DESIGN LAYOUT - Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant. | 10-02-2014 |
20150040088 | HYBRID DESIGN RULE FOR DOUBLE PATTERNING - Among other things, one or more systems and techniques for generating or implementing a hybrid design rule set are provide herein. A set of color design rules and a set of color agnostic design rules are generated and exposed for selective design rule assignment. In an embodiment, a first color design rule is assigned to a first polygon. In an embodiment, a first color agnostic design rule is assigned to a second polygon. In this way, color design rules and color agnostic design rules are selectively applied to polygons of a design layout. Color design rules are selected for space and design efficiency. Color agnostic rules are selected for conservative design layout for design ease. A design rule checking stage and a design rule fixing stage are performed such that the design layout is compliant after color decomposition without a second design rule fixing stage. | 02-05-2015 |
20150186579 | SEMICONDUCTOR DEVICE DESIGN METHOD - A method of generating a netlist comprises extracting a first capacitance value between the first set of electrical components inside a defined region using a first extraction technique. The method additionally comprises extracting a second capacitance value between a second set of electrical components comprising at least one electrical component outside the defined region using a second extraction technique different from the first extraction technique. The method also comprises generating the netlist including the first capacitance value and the second capacitance value. The first extraction technique is capable of extracting capacitance values between electrical components arranged in a first quantity of directions with respect to one another and the second extraction technique is capable of extracting capacitance values between electrical components arranged in a second quantity of directions with respect to one another. The first quantity of directions is greater than the second quantity of directions. | 07-02-2015 |
Patent application number | Description | Published |
20130021010 | DIGITAL PULSE WIDTH MODULATION CONTROLLER FOR POWER MANAGEMENT - A digital pulse width modulation (PWM) controller is used for controlling the operating voltage of an electrical load and includes a setting module, a storage module and a control module. The setting module generates control parameters corresponding to different preset load currents and load voltages of the electrical load. The storage module stores the control parameters and the prestored load current and load voltage. The control module is in electronic communication with the storage module, and detects current load voltage and current load current of the electrical load, and compares the current load voltage and load current with the prestored load voltage. Thus, the control module can output the control parameters which are necessary to stabilize the operating voltage of the electrical load, by comparison with stored data. | 01-24-2013 |
20130076334 | SELECTABLE PHASE POWER SUPPLY SYSTEM - A power supply system to provide power for a central processing unit (CPU) includes a bridge circuit, a pulse width modulation (PWM) controller and a pulse adjusting driver circuit. The bridge circuit detects a work state of the PWM controller to obtain a feedback signal output from the PWM controller, and provides the feedback signal to the CPU. The CPU outputs a control signal to the bridge circuit according to a work state of the CPU and the feedback signal, and the bridge circuit outputs a PWM signal to the pulse adjusting driver circuit according to the control signal. The pulse adjusting driver circuit receives a first driving signal provided by an external circuit, and adjusts the first driving signal according to the PWM signal to generate at least one second driving signal to drive the CPU. | 03-28-2013 |
20130086575 | APPLICATION BURNING DEVICE FOR POWER PWM CONTROLLERS AND APPLICATION BURNING METHOD - An application burning device and at least one power PWM controller are mounted on a main board. The device includes a processor and a storage unit storing applications to be burned to the at least one power PWM controller. The processor determines whether there is a power PWM controller not burned yet, and burns a corresponding application to the controller. A related application burning method is also provided. | 04-04-2013 |
Patent application number | Description | Published |
20090153263 | Modulized wave filter - A wave filter is installed in a multimedia wideband router, and includes a circuit board having a first low-pass wave-filtering circuit, and a band-pass wave-filtering circuit; the band-pass wave-filtering circuit consists of a high-pass wave-filtering circuit and a second low-pass wave-filtering circuit; the first low-pass wave-filtering circuit is connected to the high-pass wave-filtering circuit; the circuit board further includes an input terminal, and a first switching component, which is movable to such a position as to electrically connect the input terminal and a joint between the first low-pass wave-filtering circuit and the high-pass wave-filtering circuit; the circuit board further includes two output terminals, which are connected to the first and the second low-pass wave-filtering circuits respectively; a second switching component is provided on the circuit board, which is movable to such a position as to electrically connect the high-pass wave-filtering circuit and the second low-pass wave-filtering circuit. | 06-18-2009 |
20090153266 | Modulized wave filter - A wave filter includes a circuit board, and a shell housing the circuit board; the circuit board includes a band-pass wave-filtering circuit, and a low-pass wave-filtering circuit; the shell has an input end and an output terminal thereon, which are connected to the band-pass wave-filtering circuit of the circuit board; the shell further has an output end thereon, which is connected to the low-pass wave-filtering circuit; thus, the wave filter is modulized; the wave filter is fitted in a multimedia wideband router, and in turn it is not necessary to change wave filters in order for allowing the multimedia wideband router to be connected to and used with televisions or various digital multimedia equipments. | 06-18-2009 |