Patent application number | Description | Published |
20110316070 | CHARGE TRAPPING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING - The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability. | 12-29-2011 |
20120119268 | Mixed Junction Source/Drain Field-Effect-Transistor and Method of Making the Same - The present invention is related to microelectronic technologies, and discloses specifically a mixed junction source/drain field-effect-transistor and methods of making the same. The field-effect-transistor with mixed junction source/drain comprises a semiconductor substrate, a gate structure, sidewalls, and source and drain regions having mixed junction structures, which are combinations of Schottky and P-N junctions. Compared with Schottky junction field-effect-transistors, the mixed junction source/drain field-effect-transistor described in the present invention has the characteristics of relatively low source/drain leakage. At the same time, this field-effect-transistor has lower source/drain series resistances than that associated with P-N junction field-effect-transistors. | 05-17-2012 |
20120267698 | FLOATING-GATE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING - The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer. A semiconductor junction at a drain region is a P-N junction, while a semiconductor junction at a source region is a metal-semiconductor junction. | 10-25-2012 |
20120292733 | Mixed Schottky/P-N Junction Diode and Method of Making - The present invention relates to the field of microelectronic technology. It discloses a mixed Schottky/P-N junction diode and a method of making the same. The mixed Schottky/P-N junction diode comprises a semiconductor substrate having a bulk region and a doped region, and a conductive layer on the semiconductor substrate. The doped region has opposite doping from that of the bulk region. A P-N junction is formed between the bulk region and the doped region, a Schottky junction is formed between the conductive layer and the semiconductor substrate, and an ohmic contact is formed between the conductive layer and the doped region. The mixed Schottky/P-N junction diode of the present invention has high operating current, fast switching speed, small leakage current, high breakdown voltage, ease of fabrication and other advantages. | 11-22-2012 |
20130026573 | BODY CONTACT SOI TRANSISTOR STRUCTURE AND METHOD OF MAKING - The present invention puts forward a body-contact SOI transistor structure and method of making. The method comprises: forming a hard mask layer on the SOI; etching an opening exposing SOI bottom silicon; wet etching an SOI oxide layer through the opening; depositing a polysilicon layer at the opening followed by anisotropic dry etching; depositing an insulating dielectric layer at the opening followed by planarization; forming a gate stack structure by deposition and etching, and forming source/drain junctions of the transistor using ion implantation. By using the present invention, body contact for SOI field-effect transistors can be effectively formed, thereby eliminating floating-body effect in the SOI field-effect transistors, and improving heat dissipation capability of the SOI transistors and associated integrated circuits. | 01-31-2013 |
20130032881 | Asymmetric Source-Drain Field Effect Transistor and Method of Making - The present invention is related to microelectronic device technologies. A method for making an asymmetric source-drain field-effect transistor is disclosed. A unique asymmetric source-drain field-effect transistor structure is formed by changing ion implantation tilt angles to control the locations of doped regions formed by two ion implantation processes. The asymmetric source-drain field-effect transistor has structurally asymmetric source/drain regions, one of which is formed of a P-N junction while the other one being formed of a mixed junction, the mixed junction being a mixture of a Schottky junction and a P-N junction. | 02-07-2013 |
20130126954 | Dynamic Random Access Memory Array and Method of Making - The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array. | 05-23-2013 |
20130140625 | Field-Effect Transistor and Method of Making - The present invention belongs to the field of microelectronic device technologies. Specifically, an asymmetric source/drain field-effect transistor and its methods of making are disclosed. A structure of the field-effect transistor comprises: a semiconductor substrate, a gate structure, and a source region and a drain region having a mixed junction and a P-N junction, respectively. The source region and the drain region are asymmetrical structured with respect to each other, one of which comprises a P-N junction, and the other of which comprises a mixed junction, the mixed junction being a combination of a Schottky junction and a P-N junction. According to the present disclosure, a location of a doped region formed by ion implantation is controlled by adjusting an implantation angle, and a unique structure is formed for the asymmetric source/drain field-effect transistor. | 06-06-2013 |
20130270615 | METHOD FOR MAKING TRANSISTORS - A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth. | 10-17-2013 |
20130295732 | METHOD FOR MAKING FIELD EFFECT TRANSISTOR - The present invention provides a method for making a field effect transistor, comprising of the following steps: providing a silicon substrate with a first type, forming a shallow trench by photolithography and etching processes, and forming silicon dioxide shallow trench isolations inside the shallow trench; forming by deposition a high-K gate dielectric layer and a metal gate electrode layer on the substrate and the shallow trench isolations; forming a gate structure by photolithography and etching processes; forming source/drain extension regions by ion implantation of dopants of a second type; depositing an insulating layer to form sidewalls tightly adhered to the sides of the gate; forming source/drain regions and PN junction interfaces between the source/drain region and the silicon substrate by ion implantation of dopants of the second type; and performing microwave annealing to activate implanted ions. The novel process of making a field effect transistor in the present invention can achieve impurity activation in the source/drain area at a low temperature and can reduce the influence of source/drain annealing on high-K gate dielectric and metal gate electrode. | 11-07-2013 |
20140034955 | Nano-MOS Devices and Method of Making - The present invention discloses a method of making nano-MOS devices having a metal gate, thereby avoiding the poly depletion effect, and enhancing the MOS device's performance. The method forms metal gates by depositing a metal film over sidewall surfaces on two sides of a polycrystalline semiconductor layer. The metal in the metal film diffuses toward the sidewall surfaces of the polycrystalline semiconductor layer and forms, after annealing, metal-semiconductor compound nanowires (i.e., metal gates) on the sidewall surfaces of the polycrystalline semiconductor layer. Thus, high-resolution lithography is not required to form metal compound semiconductor nanowires, resulting in significant cost saving. At the same time, a nano-MOS device is also disclosed, which includes a metal gate, thereby avoiding the poly depletion effect, and resulting in enhanced MOS device performance. | 02-06-2014 |
20140034956 | Asymmetric Gate MOS Device and Method of Making - An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented. | 02-06-2014 |
20140048875 | Asymmetrical Gate MOS Device and Method of Making - An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented. | 02-20-2014 |
20140252359 | Semiconductor Device and Method of Making - The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the material in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias. | 09-11-2014 |
20140284728 | Metal Silicide Thin Film, Ultra-Shallow Junctions, Semiconductor Device and Method of Making - A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node. | 09-25-2014 |
20140306271 | Unltra-Shallow Junction Semiconductor Field-Effect Transistor and Method of Making - An ultra-shallow junction semiconductor field-effect transistor and its methods of making are disclosed. In the present disclosure, a mixture film is formed on a semiconductor substrate with a gate structure formed thereon using a physical vapor deposition (PVD) process, which employs a mixture of metal and semiconductor dopants as a target. The PVD process is followed by annealing, during which ultra-shallow junctions and ultra-thin metal silicide are formed. After removing the mixture film remaining on the semiconductor substrate, an ultra-shallow junction semiconductor field-effect transistor is formed. Because the mixture film comprises metal and semiconductor dopants, ultra-shallow junctions and ultra-thin metal silicide can be formed in a same annealing process. The ultra-shallow junction thus formed can be used in semiconductor field-effect transistors for the 14 nm, 11 nm, or even further technology node. | 10-16-2014 |
20140315366 | Semiconductor Device and Method of Making - The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias. | 10-23-2014 |