Patent application number | Description | Published |
20080209296 | Clock and Data Recovery System and Method for Clock and Data Recovery Based on a Forward Error Correction - The forward error correction based clock and data recovery system includes a data latch for intermediately storing received data, which is triggered by a sampling clock. The system further includes an error determination unit for determining whether which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal. Furthermore, the system includes a clock generator for generating the sampling clock depending on the correction signal. | 08-28-2008 |
20080284466 | Driver Circuit - A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential. | 11-20-2008 |
20090002082 | MULTIPHASE SIGNAL GENERATOR - A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage. | 01-01-2009 |
20090009154 | WIDE-BAND ANTENNA COUPLED SPECTROMETER USING CMOS TRANSISTOR - To create a broad band spectrometer, a plurality of individual antenna based bolometers are fabricated on the surface of a single spectrometer chip, each bolometer having an individual antenna which is sized differently from all others, thus being responsive to a generally unique frequency of radiation. Each antenna is coupled to a related transistor, which is easily formed using CMOS technology. The antennas are connected to opposite sides of a transistor gate, thus creating a termination resistor for the particular antenna. Multiple outputs from the various antennas are then coupled, thus providing responsiveness to electromagnetic radiation of a very broad spectrum. | 01-08-2009 |
20090039916 | Systems and Apparatus for Providing a Multi-Mode Memory Interface - An integrated circuit for a memory input/output (I/O) pin has five different modes of operation. The memory chip is enabled to operate with unbuffered (or registered) dual inline memory modules (DIMMs) as well as fully buffered DIMMs. A T-coil circuit equalizes the capacitive loading of the high-speed functions. An exemplary embodiment provides a memory chip containing a multi-functional physical I/O circuit that can act as power or ground; as a DDR2 or DDR3 interface; as a high-speed differential receiver; or as a high-speed differential transmitter. | 02-12-2009 |
20090060091 | LOW-POWER, LOW-AREA HIGH-SPEED RECEIVER ARCHITECTURE - A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators. | 03-05-2009 |
20100226241 | CROSS-TALK PROCESSING IN SERIAL LINK BUSES - A system and method for cross talk compensation in serial link busses, the method comprising: evaluating if a positive potential or a negative potential is being received by a receiver of a victim from an aggressor is dominant; measuring the distance between an incident signal and a decision threshold to obtain a positive or negative value; and using the positive or negative sign as a recovered bit value if positive potential or a negative potential is being received by a receiver of a victim from an aggressor is not dominant and using the sign of the positive potential or a negative potential that is being received by a receiver of a victim from an aggressor if this is dominant. | 09-09-2010 |
20120313703 | RESTORING OUTPUT COMMON-MODE OF AMPLIFIER VIA CAPACITIVE COUPLING - An apparatus comprises an amplifier circuit comprising at least one output node and a common-mode restoration circuit capacitively coupled to the at least one output node of the amplifier circuit. The common-mode restoration circuit is configured to introduce at least one common-mode restoring signal onto the output node, wherein the at least one common-mode restoring signal transitions in correspondence with an operation interval of the amplifier circuit and thereby compensates for a common-mode voltage drop on the at least one output node of the amplifier circuit. In one example, the amplifier circuit may comprise a current-integrating amplifier circuit, and the operation interval may comprise an integration interval. | 12-13-2012 |
20130002347 | COUPLING SYSTEM FOR DATA RECEIVERS - A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier. | 01-03-2013 |
20130322512 | RECEIVER WITH FOUR-SLICE DECISION FEEDBACK EQUALIZER - A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator latches having a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions d | 12-05-2013 |
20140070864 | CLOCK FEATHERED SLEW RATE CONTROL SYSTEM - A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate. | 03-13-2014 |
20140133604 | COUPLING SYSTEM FOR DATA RECEIVERS - A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier. | 05-15-2014 |
20140292551 | SAMPLING DEVICE WITH BUFFER CIRCUIT FOR HIGH-SPEED ADCS - A sampling and interleaving stage device for use in an analog-digital-converter and for providing a sampling output signal and an analog-to-digital-converter. The sampling and interleaving stage device for use in an analog-digital-converter, including: a receiving unit having a clock unit with a plurality of clock-driven switches for receiving an input signal; for each of the plurality of clock-driven switches, a first demultiplexer, for receiving the input signal via a clock-driven switch and for providing a number of first demultiplexer outputs; for a first demultiplexer output, at least one storage element for a stored input potential depending on the input signal; and an output demultiplexer for receiving an indication about the stored input potential and for outputting a corresponding sampling output signal to a respective sampling output. | 10-02-2014 |