Patent application number | Description | Published |
20080209285 | Method and Circuit for Measuring Operating and Leakage Current of Individual Blocks Within an Array of Test Circuit Blocks - A method and circuits for measuring operating and leakage current of individual blocks within an array of test circuit blocks provides measurement free of error due to leakage currents through non-selected circuit blocks, without requiring an independent test facility for each circuit block. The circuit includes a pair of power supply grids and selection circuits at each test circuit block to select between a test power grid and a “rest” power grid used to supply current to the non-selected circuits. The leakage currents through the non-selected circuits are thus sourced from the rest grid and error that would otherwise be introduced in the test grid current measurement is avoided. The test circuit blocks may be ring oscillators, and the measured current may be the operating and/or leakage current of the ring oscillator. The circuit blocks may also include individual devices for IV (current-voltage) characterization using an additional gate input grid. | 08-28-2008 |
20080255792 | TEST SYSTEM AND COMPUTER PROGRAM FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY - A test system and computer program for measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The test system and computer program control a characterization array circuit that imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically. | 10-16-2008 |
20080258750 | METHOD FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY - A method of measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The characterization array imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically. | 10-23-2008 |
20080258752 | METHOD AND APPARATUS FOR MEASURING DEVICE MISMATCHES - A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements. | 10-23-2008 |
20080278182 | Test Structure for Statistical Characterization of Metal and Contact/Via Resistances - A test structure for measuring resistances of a large number of interconnect elements such as metal, contacts and vias includes an array of test cells in rows and columns. Power is selectively supplied to test cells in a given column while current is selectively steered from test cells in a given row. A first voltage near the power input node of a device under test (DUT) is selectively sensed, and a second voltage near the current measurement tap is selectively sensed. The resistance of the DUT is the difference of the first and second voltages divided by the current. Additional voltage taps are provided for test cells having multiple resistive elements. This array of test cells can be used to characterize the statistical distribution of resistance variation and to identify physical location of defects in resistive elements. | 11-13-2008 |
20080281570 | Closed-Loop Modeling of Gate Leakage for Fast Simulators - A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology. | 11-13-2008 |
20080294410 | METHOD OF SEPARATING THE PROCESS VARIATION IN THRESHOLD VOLTAGE AND EFFECTIVE CHANNEL LENGTH BY ELECTRICAL MEASUREMENTS - A IC wafer is fabricated using a process of interest to have a plurality of FET devices with different channel lengths (Leff) form a plurality of channel length groups. The threshold voltage (VT) is measured of a statistical sample of the FET devices in each channel length group at two different drain-to-source voltage (VDS). The mean of VT is calculated for each channel length and each VDS. A slope coefficient λ relating VT to Leff is calculated at each VDS. The total variance of VT is calculated at each VDS. Two equations at each VDS, each relating the total variance of VT to the variance of VT with respect to dopant levels and the square of the slope coefficient λ times the variance of Leff, are solved simultaneously to obtain the variance of VT with respect to dopant levels and the variance of Leff. | 11-27-2008 |
20090031263 | METHOD AND SYSTEM FOR ANALYZING AN INTEGRATED CIRCUIT BASED ON SAMPLE WINDOWS SELECTED USING AN OPEN DETERMINISTIC SEQUENCING TECHNIQUE - Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample. | 01-29-2009 |
20090125258 | SCANNABLE VIRTUAL RAIL RING OSCILLATOR CIRCUIT AND SYSTEM FOR MEASURING VARIATIONS IN DEVICE CHARACTERISTICS - A scannable virtual rail ring oscillator circuit and system for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors. | 05-14-2009 |
20090129193 | ENERGY EFFICIENT STORAGE DEVICE USING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES - An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device. | 05-21-2009 |
20090132849 | Method and Computer Program for Selecting Circuit Repairs Using Redundant Elements with Consideration of Aging Effects - A method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects provides a mechanism for raising short-term and long-term performance of memory arrays beyond present levels/yields. Available redundant elements are used as replacements for selected elements in the array. The elements for replacement are selected by BOL (beginning-of-life) testing at a selected operating point that maximizes the end-of-life (EOL) yield distribution as among a set of operating points at which post-repair yield requirements are met at beginning-of-life (BOL). The selected operating point is therefore the “best” operating point to improve yield at EOL for a desired range of operating points or maximize the EOL operating range. For a given BOL repair operating point, the yield at EOL is computed. The operating point having the best yield at EOL is selected and testing is performed at that operating point to select repairs. | 05-21-2009 |
20090132873 | Method and System for Determining Element Voltage Selection Control Values for a Storage Device - A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization. | 05-21-2009 |
20090160463 | CHARACTERIZATION CIRCUIT FOR FAST DETERMINATION OF DEVICE CAPACITANCE VARIATION - A test circuit for fast determination of device capacitance variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter. | 06-25-2009 |
20090160477 | METHOD AND TEST SYSTEM FOR FAST DETERMINATION OF PARAMETER VARIATION STATISTICS - A method and test system for fast determination of parameter variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter. | 06-25-2009 |
20090172451 | METHOD AND COMPUTER PROGRAM FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES - A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device. | 07-02-2009 |
20090251223 | TECHNIQUES FOR CHARACTERIZING PERFORMANCE OF TRANSISTORS IN INTEGRATED CIRCUIT DEVICES - A method, system and computer program product for characterizing FET transistors in an electronic circuit (IC) device using Performance Screen Ring Oscillator (PSRO) techniques. During PSRO testing, logic and non-logic bias voltages are applied to gate terminals of the being tested FETs to determine process-related variations and the relative strength of N-type and P-type transistors. | 10-08-2009 |
20090319202 | Delay-Based Bias Temperature Instability Recovery Measurements for Characterizing Stress Degradation and Recovery - A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds. | 12-24-2009 |
20100262409 | BLENDED MODEL INTERPOLATION - According to a method of data processing, a data structure is accessed to determine a set of known data points surrounding a queried data point having an input value and an output value, the set of known data points including first, second and third data points. First and second curves are built from the first, second and third data points utilizing a first approximate model and a second approximate model. A weighting parameter value is determined by which the first curve and second curve are blended at the second data point. The output value of the queried data point is determined and stored by blending the first curve and the second curve utilizing the input value of the queried data point and the weighting parameter value. | 10-14-2010 |
20100262412 | INTEGRATED CIRCUIT MODELING BASED ON EMPIRICAL TEST DATA - In accordance with one embodiment, a plurality of empirical measurements of a fabricated integrated circuit including a fabricated transistor having multiple terminals is received. The plurality of empirical measurements each include an empirical terminal current set and an empirical terminal voltage set for the terminals of the fabricated transistor. A mathematical simulation model of a simulated transistor is also received. Utilizing the mathematical simulation model, an intermediate data set is calculated by determining, for each of a plurality of different terminal voltage sets, a simulated terminal current set and a simulated terminal charge set. A modeling tool processes the intermediate data set to obtain a time domain simulation model of the fabricated transistor that, for each of the plurality of empirical measurements, provides a simulated terminal charge set. The time domain simulation model is stored in a computer-readable data storage medium. | 10-14-2010 |
20100262413 | COMPENSATING FOR VARIATIONS IN DEVICE CHARACTERISTICS IN INTEGRATED CIRCUIT SIMULATION - According to a method of simulation data processing, a difference is determined between a simulated value of a characteristic for a simulated integrated circuit device and a corresponding empirical value of the characteristic for a fabricated integrated circuit device. A data structure containing a simulation model of the fabricated integrated circuit device is accessed, where the data structure includes a plurality of entries each accessed via a unique index and an index used to access the data structure is offset in accordance with the difference between the simulated value and the empirical value. Operation of the simulated integrated circuit device is then simulated utilizing a value obtained from one of the plurality of entries of the data structure. Results of the simulation are stored in a data storage medium. | 10-14-2010 |
20100262414 | METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS - Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area. | 10-14-2010 |
20100313070 | BROKEN-SPHERES METHODOLOGY FOR IMPROVED FAILURE PROBABILITY ANALYSIS IN MULTI-FAIL REGIONS - A failure probability for a system having multi-fail regions is computed by generating failure directions in a space whose dimensions are the system parameters under consideration. The failure directions are preferably uniform, forming radial slices. The failure directions may be weighted. The radial slices have fail boundaries defining fail regions comparable to broken shells. The distribution of the system parameters is integrated across the broken shell regions to derive a failure contribution for each failure direction. The failure probability is the sum of products of each failure contribution and its weight. Failure contributions are computed using equivalent expressions dependent on the number of dimensions, which can be used to build lookup tables for normalized fail boundary radii. The entire process can be iteratively repeated with successively increasing failure directions until the failure probability converges. The method is particularly useful in analyzing failure probability of electrical circuits such as memory cells. | 12-09-2010 |
20100333049 | Model-Based Retargeting of Layout Patterns for Sub-Wavelength Photolithography - Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations until a counter value exceeds a maximum predetermined number of iterations in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes in response to the counter value exceeding the maximum predetermined number of iterations. A normalized image log slope (NILS) extraction is performed on the set of target shapes and use the set of lithographic contours to produce NILS values. The set of target patterns is modified based on the NILS values in response to the NILS values failing to be within a predetermined limit. The steps are repeated until the NILS values are within the predetermined limit. | 12-30-2010 |
20110035709 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 02-10-2011 |
20110054856 | Equivalent Device Statistical Modeling for Bitline Leakage Modeling - Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device. | 03-03-2011 |
20110074394 | TEST CIRCUIT FOR BIAS TEMPERATURE INSTABILITY RECOVERY MEASUREMENTS - A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds. | 03-31-2011 |
20110154271 | Optical Proximity Correction for Improved Electrical Characteristics - A method, computer program product, and data processing system for performing an improved optical proximity correction are disclosed, which better respect the electrical properties of the device being manufactured. A preferred embodiment of the present invention performs OPC by first dividing the perimeter of a mask region into a plurality of segments, then grouping the segments into at least two distinct groups, wherein segments in the first of these groups are adjusted in position so as to minimize edge placement error (EPE) when the photolithography using the mask is simulated. Segments in the second group are adjusted in position so as to minimize cumulative error in a dimension spanning the region, wherein the span of such dimension extends from segments in the first group to segments in the second group. Correction so obtained by this process more readily preserves the intended electrical behavior of the original device design. | 06-23-2011 |
20110225438 | COMPUTER PROGRAM PRODUCT FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES - A computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device. | 09-15-2011 |
20120046929 | Statistical Design with Importance Sampling Reuse - A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios. | 02-23-2012 |
20120110521 | Split-Layer Design for Double Patterning Lithography - A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker. | 05-03-2012 |
20120260221 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 10-11-2012 |
20120262187 | TEST CIRCUIT FOR BIAS TEMPERATURE INSTABILITY RECOVERY MEASUREMENTS - A method and test circuit provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds. | 10-18-2012 |
20120266111 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 10-18-2012 |
20120266112 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 10-18-2012 |
20120266113 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 10-18-2012 |
20120266114 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 10-18-2012 |
20120278769 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 11-01-2012 |
20120293197 | On-Chip Leakage Current Modeling and Measurement Circuit - At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit. | 11-22-2012 |
20120317523 | Reducing Through Process Delay Variation in Metal Wires - A mechanism is provided for reducing through process delay variation in metal wires by layout retargeting. The mechanism performs initial retargeting, decomposition, and resolution enhancement techniques. For example, the mechanism may perform optical proximity correction. The mechanism then performs lithographic simulation and optical rules checking. The mechanism provides retargeting rules developed based on coupling lithography simulation and resistance/capacitance (RC) extraction. The mechanism performs RC extraction to capture non-linear dependency of RC on design shape dimensions. If the electrical properties in the lithographic simulation are within predefined specifications, the mechanism accepts the retargeting rules; however, if the electrical properties from RC extraction are outside the predefined specifications, the mechanism modifies the retargeting rules and repeats resolution enhancement techniques. | 12-13-2012 |
20120317529 | Rapid Estimation of Temperature Rise in Wires Due to Joule Heating - A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations. | 12-13-2012 |
20120319674 | CALIBRATION OF NON-CONTACT CURRENT SENSORS - Calibration of a non-contact current sensor provides improved accuracy for measuring current conducted through a conductor such as an AC branch circuit wire. In a calibration mode, a predetermined current is injected through a voltage sensing conductor integrated in the non-contact current sensor. The magnitude of the magnetic field is measured using a sensing element of the non-contact current sensor. Then, when operating in measurement mode, a current conducted in a wire passing through the non-contact current sensor is determined by correcting the output of the non-contact current sensor using the result of the measurement made in the calibration mode. The voltage sensing conductor is used to provide an indication of the magnitude and/or the phase of the electrostatic potential on the wire. The calibration current may be a DC current, and calibration may be performed while the conductor is carrying an AC current. | 12-20-2012 |
20120319675 | CALIBRATION OF NON-CONTACT VOLTAGE SENSORS - Calibration of a non-contact voltage sensor provides improved accuracy for measuring voltage on a conductor such as an AC branch circuit wire. In a calibration mode, a predetermined voltage is imposed on a first voltage sensing conductor integrated in the non-contact voltage sensor, while a voltage on a second voltage sensing conductor is measured using a circuit of predetermined input impedance. The capacitance between the wire and each of the voltage sensing conductors may be the same, so that in measurement mode, when the first and second voltage sensing conductors are coupled together, the effective series capacitance provided in combination with the predetermined input impedance is four times as great. The results of the voltage measurement made in the calibration mode can thereby be used to adjust subsequent voltage measurements made in measurement mode with the first and second voltage sensing conductors combined in parallel. | 12-20-2012 |
20130014069 | Equivalent Device Statistical Modeling for Bitline Leakage Modeling - Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device. | 01-10-2013 |
20130061183 | Multiple Patterning Layout Decomposition for Ease of Conflict Removal - A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction, The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features, The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors. | 03-07-2013 |
20130061185 | MASK ASSIGNMENT FOR MULTIPLE PATTERNING LITHOGRAPHY - A mechanism is provided for mask assignment for triple patterning lithography. The mechanism identifies tip-to-tip (TT), tip-to-side (TS), and side-to-side (SS) conflicting parts by design rule dependent projection. The mechanism finds stitch location for TT, TS, and SS conflicts separately. The mechanism colors TT, TS, and SS conflicting parts with mask0/mask1, mask0/mask2, mask1/mask2 coloring cycle with each type colored separately. The mechanism uses existing infrastructure of two-way coloring. As a first objective, the mechanism attempts to minimize conflicts. As a second objective, the mechanism attempts to minimize the number of stitches by assigning the two sides of stitches to the same mask. Once coloring of all conflicting parts is done, the mechanism colors non-conflicting parts to maximize minimum overlap of exposures and to use both colors if two sides are different colors and one color if both sides are the same color. | 03-07-2013 |
20130212444 | METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS - Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area. | 08-15-2013 |
20130241529 | CALIBRATION OF NON-CONTACT CURRENT SENSORS - Calibration of a non-contact current sensor provides improved accuracy for measuring current conducted through a conductor such as an AC branch circuit wire. In a calibration mode, a predetermined DC current is injected through a conductor integrated in the non-contact current sensor. The magnitude of the magnetic field is measured using a sensing element of the non-contact current sensor. Then, when operating in measurement mode, a current conducted in a wire passing through the non-contact current sensor is determined by correcting the output of the non-contact current sensor using the result of the measurement made in the calibration mode. | 09-19-2013 |
20140100804 | Statistical Determination of Power-Circuit Connectivity - A mechanism is provided for statistical determination of power circuit connectivity based on signal detection in a circuit. Signal data from the circuit gathered and a determination is made as to whether a signal of interest is present in the gathered signal data from the circuit using a statistical analysis of the gathered signal data. The statistical analysis comprises using a mean current value and statistical deviation of the current value of the signal data over a predetermined period of time to compute a confidence range. The confidence range is compared to a first threshold and a second threshold. A determination is made that the signal is present in response to the confidence range being above the first threshold. A determination is made that the signal is not present in response to the confidence range being below the second threshold. | 04-10-2014 |
20140215274 | Statistical Design with Importance Sampling Reuse - A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios. | 07-31-2014 |
20150066467 | POWER AND PERFORMANCE SORTING OF MICROPROCESSORS FROM FIRST INTERCONNECT LAYER TO WAFER FINAL TEST - A system, method and computer program product for sorting Integrated Circuits (chips), particularly microprocessor chips, and particularly that predicts chip performance or power for sorting purposes. The system and method described herein uses a combination of performance-predicting parameters that are measured early in the process, and applies a unique method to project where the part, e.g., microprocessor IC, will eventually be sorted. Sorting includes classifying the IC product to a subset of a family of products with the product satisfying certain performance characteristics or specifications, in the early stages of manufacturing, e.g., before the end product is fully fabricated. | 03-05-2015 |