Patent application number | Description | Published |
20150179256 | Memory Systems and Memory Programming Methods - Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline. | 06-25-2015 |
20150194212 | Memory Systems and Memory Programming Methods - Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic. | 07-09-2015 |
20160118119 | Memory Programming Methods and Memory Systems - Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described. | 04-28-2016 |
Patent application number | Description | Published |
20080209284 | Input/output compression and pin reduction in an integrated circuit - An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock. | 08-28-2008 |
20090040837 | System and method for reducing pin-count of memory devices, and memory device testers for same - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 02-12-2009 |
20090238009 | SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 09-24-2009 |
20100205490 | INPUT/OUTPUT COMPRESSION AND PIN REDUCTION IN AN INTEGRATED CIRCUIT - An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock. | 08-12-2010 |
20120008404 | SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 01-12-2012 |
20140112052 | Memory Programming Methods And Memory Systems - Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described. | 04-24-2014 |
20140293674 | RRAM, and Methods of Storing and Retrieving Information for RRAM - Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another. | 10-02-2014 |
Patent application number | Description | Published |
20120218807 | RESISTIVE MEMORY SENSING METHODS AND DEVICES - The present disclosure includes resistive memory sensing methods and devices. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing an indication of those cells of the group that conduct at least a threshold amount of current responsive to one of a number of different sense voltages successively applied to the selected conductive line during each of a corresponding number of the multiple passes, and for each successive pass of the multiple passes, disabling data lines corresponding to those cells determined to have conducted the threshold amount of current in association with a previous one of the multiple passes. | 08-30-2012 |
20130229878 | SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 09-05-2013 |
20140233298 | APPARATUS AND METHODS FOR FORMING A MEMORY CELL USING CHARGE MONITORING - Apparatuses and methods of forming a memory cell is described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring. | 08-21-2014 |
20140340952 | APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD - An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to faun a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates. | 11-20-2014 |
20160118405 | APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD - An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates. | 04-28-2016 |
Patent application number | Description | Published |
20130294148 | RESISTIVE MEMORY SENSING METHODS AND DEVICES - The present disclosure includes resistive memory sensing methods and devices. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing an indication of those cells of the group that conduct at least a threshold amount of current responsive to one of a number of different sense voltages successively applied to the selected conductive line during each of a corresponding number of the multiple passes, and for each successive pass of the multiple passes, disabling data lines corresponding to those cells determined to have conducted the threshold amount of current in association with a previous one of the multiple passes. | 11-07-2013 |
20140169066 | RESISTIVE MEMORY SENSING - The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal. | 06-19-2014 |
20150124517 | APPARATUS AND METHODS FOR FORMING A MEMORY CELL USING CHARGE MONITORING - Apparatus and methods of forming a memory cell are described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring. | 05-07-2015 |
20150255153 | RESISTIVE MEMORY SENSING - The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal. | 09-10-2015 |
20160035406 | FIXED VOLTAGE SENSING IN A MEMORY DEVICE - Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell. | 02-04-2016 |
Patent application number | Description | Published |
20130200118 | MULTI-FUNCTIONAL HOLSTER FOR ELECTRONIC DEVICE - A multi-purpose holster attaches to surfaces/objects, to retain an electronic device in a desirable position for hands-free use as a camera or video recorder. An elastic first strap extends transversely from a main body of the holster, wraps around the electronic device and fastens to itself to capture the device in portrait orientation. An elastic second strap extends parallel to the main body and around the electronic device, and fastens to the rear of the main body or to a portion of the first strap to capture the device in landscape orientation. The holster may include suction cup, loop and/or other suspension mechanisms to suspend the holster from the vertical surface of other object, and/or the first and second straps may be used to strap the holster to the surface/object. | 08-08-2013 |
20130270129 | Multi-Functional Pouch for Transporting and/or Suspending an Electronic Device - A multi-purpose carrying pouch attaches to surfaces/objects, to retain an electronic device in a desirable position for hand-free use as a camera or video recorder. An upper bi-fold flap with integrated suction cup unfolds and extends upwards from a main body of the pouch. The main pouch compartment is opened/unzipped to allow the electronic device to be stored, or to be inserted in an upright position with both zipper-sliders moved to a central region along the zipper near the device to capture the device in portrait orientation. An elastic strap extends transversely from a zipper pocket formed in the pouch, wraps around the electronic device, and fastens to a lower bi-fold flap to capture the device in landscape orientation. The zipper pocket and strap may be located in various locations, for example, on the interior or exterior surface of the pouch. | 10-17-2013 |
20130306689 | Head Mount Apparatus For Hands-Free Video Recording With An Electronic Device - A head mount device is worn by a person to retain an electronic device in a desirable position for hand-free use as a video recorder. A head strap assembly with tri-glide adjustment mechanisms extends from the sides and top of the main body mounting plate, allowing the device to fit most head sizes. The mounting plate is preferably an injection-molded part for holding the electronic device in a horizontal position with an elastic retention strap securing mechanism between the mounting plate and the electronic device. An elastic strap extends from an upending portion of the mounting plate, wraps around the electronic device, extends through a slot in the mounting plate, and fastens back upon itself via hook and loop fasteners to capture the device in landscape orientation. The design of the mounting plate and preferred length of the retention strap fit most modern smartphone designs by simply tightening the retention strap around the smartphone. | 11-21-2013 |
20130341412 | MULTIPLE SUCTION CUP STORED-VALUE CARD FOR SECURING AN ELECTRONIC DEVICE ON A SURFACE - A mounting apparatus permits easy and quick attachment and removal of a portable electronic device to smooth surfaces for self-photos or videos, for example. A flat panel/card holds multiple, mini, double-sided suction cup units. One side of each cup unit may be connected to a portable electronic device such as a smart phone, or other lightweight digital media device with a smooth LCD or touch screen. The other side of each cup unit may be connected to a generally vertical surface or other object. The panel/card may be a single-layer plastic card with retention slots into which the double-sided suction cups are inserted. The panel/card may also function as a stored-value card, pre-paid gift card, or credit card incorporating bar codes, scratch-off codes, and magnetic strip features. | 12-26-2013 |
20150070839 | MULTIPLE SUCTION CUP ATTACHMENT PLATFORM: SECURING AN ELECTRONIC DEVICE ON A VERTICAL SURFACE - A mounting apparatus permits easy and quick attachment and removal of the apparatus securing a portable device to smooth surfaces, or objects. An injection molded platform which allows multiple suction cups to be attached to secure a portable electronic device such as a smart phone, cellular phone, tablet, e-reader, or other digital media device to a smooth surface, or object. The primary platform is an injection molded part specifically designed to accommodate the insertion of mini suction cups, small suction cups, and medium suction cups. The injection molded platform contains multiple openings specifically designed to allow the attachment of an array of suction cups, and alternative mechanisms including kickstand assembly, elastic straps or cording. It is a further object of the invention to provide a platform apparatus that can be attached to smooth surfaces for different sized devices with touch screen capabilities, and devices with camera and video functions. | 03-12-2015 |
Patent application number | Description | Published |
20090153205 | METHODS, DEVICES, AND SYSTEMS FOR A DELAY LOCKED LOOP HAVING A FREQUENCY DIVIDED FEEDBACK CLOCK - Methods, devices, and systems are disclosed for a delay locked loop. A delay locked loop may comprise a delay line configured to receive a reference clock signal and output a delayed clock signal. The delay locked loop may also comprise a feedback loop including a frequency divider operably coupled to the delayed clock signal and configured to generate a frequency divided clock signal. Furthermore, the delay locked loop may include a phase detector configured to receive the reference clock signal and the frequency divided clock signal having a frequency less than that of the reference clock signal. Additionally, the phase detector may be configured to measure a phase difference of the reference clock signal and the frequency divided clock signal upon receipt of an active edge of the frequency divided clock signal. | 06-18-2009 |
20110219256 | SYNCHRONIZATION DEVICES HAVING INPUT/OUTPUT DELAY MODEL TUNING ELEMENTS IN SIGNAL PATHS TO PROVIDE TUNING CAPABILITIES TO OFFSET SIGNAL MISMATCH - Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in the signal path of the synchronization device. The tuning elements are designed to be identical, such that a single design may be used to a signal mismatch that is produced in either direction, using a single design. The tuning elements may be implemented to provide uniformity in the access time through a range of conditions, such as drain voltages and temperatures. | 09-08-2011 |
Patent application number | Description | Published |
20090296495 | SYSTEM AND METHOD FOR CAPTURING DATA SIGNALS USING A DATA STROBE SIGNAL - A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal. | 12-03-2009 |
20090300314 | MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING READ DATA - Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface. | 12-03-2009 |
20100014364 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 01-21-2010 |
20110044116 | SYSTEM AND METHOD FOR CAPTURING DATA SIGNALS USING A DATA STROBE SIGNAL - A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal. | 02-24-2011 |
20110075497 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 03-31-2011 |
20110296227 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 12-01-2011 |
20130117628 | SELF-TIMED ERROR CORRECTING CODE EVALUATION SYSTEM AND METHOD - Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates. | 05-09-2013 |
20130318298 | MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING READ DATA - Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface. | 11-28-2013 |
20130346722 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 12-26-2013 |
20140040696 | SELF-TIMED ERROR CORRECTING CODE EVALUATION SYSTEM AND METHOD - Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates. | 02-06-2014 |
20140258666 | MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING READ DATA - Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface. | 09-11-2014 |
20140337570 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 11-13-2014 |
Patent application number | Description | Published |
20110151073 | Systems and Methods for Ozone Treatment of Grain in Grain Piles - Systems and methods for treating grain stored in a grain pile with ozone are effective for treating grain for toxins, insects, mold, and/or odor. A method according to embodiments of the invention involves monitoring at least one of temperature and odor at a plurality of aeration outlet locations spaced around the grain pile. When an abnormal temperature variance or odor is detected at one or more of the aeration outlet locations, a determination is made as to a problem location within the grain pile where a treatment of ozone should be applied, and a further determination is made as to how best to apply ozone to the problem location. Ozone is then applied to the problem location within the grain pile to minimize nascent problems in the grain pile. The ozone treatment may reduce molds and toxins. | 06-23-2011 |
20110151079 | Systems and Methods for Continuous Flow Ozone Treatment of Grain - Methods and systems for treatment of grain for toxins and/or odor utilize a storage container having a grain storage space and an aeration floor that allows air to flow through the aeration floor into the grain storage space. Ozone (mixed with air) is supplied to the grain through the aeration floor under positive pressure, whereby ozone is forced through the aeration floor into a lower portion of the grain storage space. After an initial treatment time, the initial treatment time allowing for the ozone to reduce toxins and/or odor in a lowermost portion of the initial quantity of grain an effective or desired amount, a lowermost portion or a lower treated portion of the grain in the grain storage space is removed, and new grain is added on top of the grain in the grain storage space, all while continuing to supply ozone through the aeration floor under positive pressure. | 06-23-2011 |
20110151080 | Systems and Methods for Ozone Treatment of Toxin in Grain - Methods and systems for treatment of grain in a storage container using ozone may be used for treating grain for toxins, insects, mold, and/or odor. Downdraft methods for applying high concentrations of ozone to grain in a storage container treat grain without generating ozone-related objectionable odors or with generation of only minimal ozone-related objectionable odors. A method for downdraft ozone treatment of grain with minimal generation of ozone-related objectionable odors involves providing a negative air pressure at a bottom of a volume of grain in a storage container. A high ozone concentration is generated in air above an upper surface of the volume of grain. The ozone is drawn down into the volume of grain using the negative air pressure for a treatment time sufficient to effectively treat the grain without causing significant ozone-related commercially-objectionable foreign odors in the grain. | 06-23-2011 |
Patent application number | Description | Published |
20110151073 | Systems and Methods for Ozone Treatment of Grain in Grain Piles - Systems and methods for treating grain stored in a grain pile with ozone are effective for treating grain for toxins, insects, mold, and/or odor. A method according to embodiments of the invention involves monitoring at least one of temperature and odor at a plurality of aeration outlet locations spaced around the grain pile. When an abnormal temperature variance or odor is detected at one or more of the aeration outlet locations, a determination is made as to a problem location within the grain pile where a treatment of ozone should be applied, and a further determination is made as to how best to apply ozone to the problem location. Ozone is then applied to the problem location within the grain pile to minimize nascent problems in the grain pile. The ozone treatment may reduce molds and toxins. | 06-23-2011 |
20110151079 | Systems and Methods for Continuous Flow Ozone Treatment of Grain - Methods and systems for treatment of grain for toxins and/or odor utilize a storage container having a grain storage space and an aeration floor that allows air to flow through the aeration floor into the grain storage space. Ozone (mixed with air) is supplied to the grain through the aeration floor under positive pressure, whereby ozone is forced through the aeration floor into a lower portion of the grain storage space. After an initial treatment time, the initial treatment time allowing for the ozone to reduce toxins and/or odor in a lowermost portion of the initial quantity of grain an effective or desired amount, a lowermost portion or a lower treated portion of the grain in the grain storage space is removed, and new grain is added on top of the grain in the grain storage space, all while continuing to supply ozone through the aeration floor under positive pressure. | 06-23-2011 |
20110151080 | Systems and Methods for Ozone Treatment of Toxin in Grain - Methods and systems for treatment of grain in a storage container using ozone may be used for treating grain for toxins, insects, mold, and/or odor. Downdraft methods for applying high concentrations of ozone to grain in a storage container treat grain without generating ozone-related objectionable odors or with generation of only minimal ozone-related objectionable odors. A method for downdraft ozone treatment of grain with minimal generation of ozone-related objectionable odors involves providing a negative air pressure at a bottom of a volume of grain in a storage container. A high ozone concentration is generated in air above an upper surface of the volume of grain. The ozone is drawn down into the volume of grain using the negative air pressure for a treatment time sufficient to effectively treat the grain without causing significant ozone-related commercially-objectionable foreign odors in the grain. | 06-23-2011 |
Patent application number | Description | Published |
20090057848 | REDISTRIBUTION STRUCTURES FOR MICROFEATURE WORKPIECES - Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line. | 03-05-2009 |
20100044876 | CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES - Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate. | 02-25-2010 |
20100258939 | STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS - Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device. | 10-14-2010 |
20110147910 | METHOD FOR STACKING DIE IN THIN, SMALL-OUTLINE PACKAGE - Several embodiments of microelectronic device packaging configurations with lead frames without downsets are disclosed herein. In one embodiment, the configuration includes a pair of microelectronic dies with active surfaces facing one another, and a lead frame positioned between the dies. The lead frame has no downset and extends from between the dies and protrudes out of an encapsulant material. In one embodiment the lead frame is connected to both an upper and a lower die. In other embodiments, the lead frame is connected to a first die by wirebonds and is not connected to a second die. The first and second die may be connected to one another by interconnects such as solder ball interconnects. | 06-23-2011 |
20120302054 | CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES - Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate. | 11-29-2012 |
20130217183 | STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS - Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device. | 08-22-2013 |
20150145593 | REDISTRIBUTION STRUCTURES FOR MICROFEATURE WORKPIECES - Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line. | 05-28-2015 |
Patent application number | Description | Published |
20100072268 | Insulated beverage container - The insulated beverage container is a container, such as a coffee cup, providing thermal insulation for the user's hand. The container includes a vertically extending annular wall and a base, forming a beverage-receiving cup. A plurality of tubes are secured to an outer surface of the annular wall. Each tube is hollow and defines an air passage therein, and is further elongated along the vertical direction, having upper and lower air flow apertures formed therethrough. In use, heat generated by the beverage heats the air contained within the tubes. As the air rises within the tubes, ambient air at a lower temperature is drawn through the lower air flow apertures and the heated air is expelled through the upper air flow apertures, maintaining a flow of cooled air from the environment through the tubes. | 03-25-2010 |
20110056806 | Spiral Conveyor System and Methods - A double-helix spiral conveyor, a method for conveying articles up and down a spiral conveyor, and a method for constructing a drive drum for a spiral conveyor. The double-helix spiral conveyor conveys articles on the conveyor up the inner side of a spiral drum by engaging the outer edge of the belt and down the outer side of the drum by engaging the inner edge of the belt. A slew drive at the bottom of the drum drives the conveyor. | 03-10-2011 |
20110174596 | SPIRAL BELT CONVEYOR - The spiral belt conveyor is a conveyor belt system for trans-porting articles vertically along a helical path. The spiral belt conveyor includes a platform and a central frame structure extending upwardly from the platform. Two idler rollers are mounted on the platform. A helical track having an inner portion and an outer portion is concentrically disposed around the shaft. The inner portion of the helical track has a first radius, and the outer portion thereof has a second radius greater than the first radius. An upper end of the inner portion of the helical track meets an upper end of the outer portion of the helical track adjacent an upper end of the central frame structure. A conveyor belt is mounted on the helical track and the pair of idler rollers. | 07-21-2011 |
Patent application number | Description | Published |
20130146676 | Recapture Sprayer Shell - The present disclosure relates to a system and method for spraying a target object. A recapture shell may partially contain the target object and mitigate dispersal of overspray. A leading front of higher-than ambient air pressure and a trailing front of lower-than ambient air pressure are created to partially isolate recirculating air within a target space in the recapture shell to enhance spray coverage and mitigate spray loss. Embodiments of the present disclosure may be used for agricultural, automotive, aerospace, and other applications to emit, contain, and/or recapture a spray. | 06-13-2013 |
20130146678 | Recapture Sprayer - The present disclosure relates to a system and method for spraying one or more target objects. A primary blower system is adapted to create a relatively isolated field of circulating air by creating a primary air stream around the field of circulating air. A secondary blower system is adapted to circulate air within the isolated field by flowing a secondary air stream in directions contrary to the primary air stream. A chemical spray comprising liquid, aerosol droplets, particulate matter, or the like may be emitted into the circulating air within the field and thereby deposited on target objects within the field. Embodiments of the present disclosure may be used for agricultural, automotive, aerospace, and other applications to emit, contain, and/or recapture a spray. | 06-13-2013 |
Patent application number | Description | Published |
20090160990 | Imager method and apparatus having combined select signals - An imaging device and method for operating the device. The device comprises a pixel array having a plurality of pixels arranged in rows and columns and a plurality of readout circuits for the pixels. A reset circuit in one readout circuit is simultaneously operated with a row select circuit in another readout circuit using a common select line. A transfer select circuit may also be simultaneously operated with the common select line. | 06-25-2009 |
20090237540 | Imager method and apparatus having combined gate signals - An imaging device and method for operating the device. The device comprises a pixel array having a plurality of pixels arranged in rows and columns and a plurality of readout circuits for the pixels. A reset circuit in one readout circuit is simultaneously operated with a dual conversion gain select circuit in another readout circuit using a common select line. Alternatively, a row circuit in one readout circuit is simultaneously operated with a dual conversion gain select circuit in another readout circuit using a common select line. | 09-24-2009 |
20090237541 | Method and apparatus providing reduced metal routing in imagers - An imaging device and method for operating the device. The imaging device comprises a pixel array having a plurality of pixels arranged in rows and columns. At least one pixel of the array comprises a photosensor and a first reset circuit responsive to a first reset control signal for resetting the photosensor. A first terminal of the first reset circuit is coupled to the photosensor and a second terminal of the first reset circuit is configured to receive a first resetting voltage from a control line. | 09-24-2009 |
20100118167 | METHODS AND APPARATUS PROVIDING SELECTIVE BINNING OF PIXEL CIRCUITS - A pixel circuit configured for optionally connecting the floating diffusion region of the pixel circuit to a floating diffusion region of another pixel circuit. Methods of using the pixel circuit include averaging or summing multiple photosensor outputs in the combined floating diffusion regions, varying the conversion gain of a pixel circuit floating diffusion region, and utilizing multiple readout circuits to readout charges transferred from a single photosensor to the combined floating diffusion regions. A method of window-of-interest averaging that utilizes the combined floating diffusion regions is also disclosed. | 05-13-2010 |
Patent application number | Description | Published |
20090002508 | Method and apparatus for dark current reduction in image sensors - Methods and apparatuses for dark current reduction by adjustment of electrical characteristics of transfer gates in pixels within an imaging sensor based on image comparisons. | 01-01-2009 |
20090127436 | METHOD AND APPARATUS FOR CONTROLLING ANTI-BLOOMING TIMING TO REDUCE EFFECTS OF DARK CURRENT - An electronic imager includes a plurality of pixels having photosensors for accumulating charge corresponding to individual pixel values of a sensed image. Each of the pixels includes an anti-blooming function which allows charge in excess of a predetermined amount to be drained from the photosensor thus reducing the charge from the pixel that migrates to adjacent pixels. The imager also includes circuitry which controls the anti-blooming function in response to image intensity to reduce dark current in the imager caused by the anti-blooming function. | 05-21-2009 |
20090207284 | METHOD AND APPARATUS FOR CONTROLLING ANTI-BLOOMING TIMING TO REDUCE EFFECTS OF DARK CURRENT - An electronic imager includes a plurality of pixels having photosensors for accumulating charge corresponding to individual pixel values of a sensed image. Each of the pixels includes an anti-blooming function which allows charge in excess of a predetermined amount to be drained from the photosensor thus reducing the charge from the pixel that migrates to adjacent pixels. The imager also includes circuitry which controls the anti-blooming function in response to image intensity to reduce dark current in the imager caused by the anti-blooming function. | 08-20-2009 |
20120188415 | DIGITALLY GRADED NEUTRAL DENSITY FILTER - Apparatus and a method for performing neutral density filtering in a digital camera. The camera includes a pixel array having rows and columns of pixels. The pixels in the array may be reset and read with variable timing between the reset operation and the read operation. The timing between the reset and read operations is controlled to implement a neutral density filtering operation. | 07-26-2012 |
20120193515 | IMAGERS WITH DEPTH SENSING CAPABILITIES - An imager may include depth sensing pixels that provide an asymmetrical angular response to incident light. The depth sensing pixels may each include a substrate region formed from a photosensitive portion and a non-photosensitive portion. The depth sensing pixels may include mechanisms that prevent regions of the substrate from receiving incident light. Depth sensing pixel pairs may be formed from depth sensing pixels that have different asymmetrical angular responses. Each of the depth sensing pixel pairs may effectively divide the corresponding imaging lens into separate portions. Depth information for each depth sensing pixel pair may be determined based on the difference between output signals of the depth sensing pixels of that depth sensing pixel pair. The imager may be formed from various combinations of depth sensing pixel pairs and color sensing pixel pairs arranged in a Bayer pattern or other desired patterns. | 08-02-2012 |
20130020467 | IMAGING SYSTEMS WITH COLUMN CURRENT MIRROR CIRCUITRY - Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to an active and an inactive current supply circuit. Each active current supply circuit may form a portion of a current mirror circuit that includes a common current source and a common input transistor. Each active current supply circuit may include a mirror transistor for mirroring current that flows through the common input transistor and a permanently enabled enabling transistor for activating that mirror transistor. Mirrored current that flows through a particular active mirror transistor may be supplied to image pixels in the pixel column associated with that particular mirror transistor. Each inactive current supply circuit may include a mirror transistor coupled to the input transistor and a permanently disabled enabling transistor. | 01-24-2013 |
20140094993 | IMAGING SYSTEMS WITH VERIFICATION PIXELS - An imaging system may include a pixel array having a plurality of image pixels and a plurality of test pixels. The test pixels may each include a photodiode configured to receive a test voltage. For example, the photodiodes of test pixels may be coupled to a bias voltage supply line or the photodiodes may receive test voltages via a column readout line or a row control line. The test voltage may be output on a column line associated with the column of pixels in which the test pixel is located. Verification circuitry may compare the output test signal with a predetermined reference signal to determine whether the imaging system is functioning properly. If an output test signal does not match the expected output signal, the imaging system may be disabled and/or a warning signal may be presented to a user of the system. | 04-03-2014 |
20140263980 | IMAGERS WITH DEPTH SENSING CAPABILITIES - An imager may include depth sensing pixels that provide an asymmetrical angular response to incident light. The depth sensing pixels may each include a substrate region formed from a photosensitive portion and a non-photosensitive portion. The depth sensing pixels may include mechanisms that prevent regions of the substrate from receiving incident light. Depth sensing pixel pairs may be formed from depth sensing pixels that have different asymmetrical angular responses. Each of the depth sensing pixel pairs may effectively divide the corresponding imaging lens into separate portions. Depth information for each depth sensing pixel pair may be determined based on the difference between output signals of the depth sensing pixels of that depth sensing pixel pair. The imager may be formed from various combinations of depth sensing pixel pairs and color sensing pixel pairs arranged in a Bayer pattern or other desired patterns. | 09-18-2014 |
20150244950 | IMAGE SENSOR SYSTEMS AND METHODS FOR MULTIPLE EXPOSURE IMAGING - An imaging device may capture a composite image from multiple individual exposures. In each imaging pixel in the imaging device, charge accumulated from each of the individual exposures may be accumulated onto a storage node. The accumulated charge from all of the individual exposures in a single composite image may be read out from the storage node. The individual exposures may be separated by delay periods. The lengths of the individual exposures and delay periods may be determined automatically or set by a user such that each individual exposure is substantially free of motion blur, while the composite image illustrates a moving subject in multiple positions. | 08-27-2015 |
20150319420 | IMAGING SYSTEMS WITH PHASE DETECTION PIXELS - An image sensor may include phase detection pixels that receive and convert incident light into pixel signals. Processing circuitry may use pixel signals from the phase detection pixels to determine an amount by which image sensor optics should be adjusted during automatic focusing operations. Phase detection pixels may include photodiodes with asymmetric angular responses. For example, the center of a photodiode in a phase detection pixel may be offset from the optical center of the microlens that covers that photodiode. A group of two, three, four, or more than four phase detection pixels may be clustered together and covered by a single microlens. Groups of these clusters may be arranged consecutively in a line. Phase data may be gathered using all of the phase detection pixels in the array, and image processing circuitry may determine which phase data to use after the data has been gathered. | 11-05-2015 |
20150381907 | IMAGING SYSTEMS FOR INFRARED AND VISIBLE IMAGING WITH PATTERNED INFRARED CUTOFF FILTERS - An image sensor may include a pixel array having visible and infrared imaging pixels for simultaneously detecting light in the visible and infrared spectral ranges. The pixel array may include an array of photodiodes, an array of filter elements formed over the photodiodes, and an array of microlenses formed over the array of filter elements. The filter elements may include infrared cutoff filter elements that block infrared light while passing visible light. The infrared cutoff filter elements may be formed from a patterned layer of infrared blocking material. Each visible imaging pixel includes a portion of the infrared blocking material and a color filter element. Each infrared imaging pixel is aligned with an opening in the infrared blocking material. The opening may be filled with an infrared pass filter element that passes infrared light while blocking visible light. | 12-31-2015 |
20160065821 | IMAGING SYSTEMS AND METHODS FOR CAPTURING IMAGE DATA AT HIGH SCAN RATES - An imaging system may include a rolling shutter image sensor, data rate reduction circuitry, and image processing circuitry. The image sensor may output image data to the data rate reduction circuitry at a first high speed data rate. The data rate reduction circuitry may store the image data at the first data rate and may output the stored image data at a second reduced speed data rate. The image processing circuitry may receive the image data at the second data rate and may perform image processing operations at the second data rate. The data rate reduction circuitry may generate accumulated image frames by accumulating image frames received from the image sensor at the first data rate and may provide the accumulated frames to the image processing circuitry at the second data rate. The image processing circuitry may perform image processing operations on the accumulated frames at the second data rate. | 03-03-2016 |
20160099273 | IMAGERS WITH DEPTH SENSING CAPABILITIES - An imager may include depth sensing pixels that provide an asymmetrical angular response to incident light. The depth sensing pixels may each include a substrate region formed from a photosensitive portion and a non-photosensitive portion. The depth sensing pixels may include mechanisms that prevent regions of the substrate from receiving incident light. Depth sensing pixel pairs may be formed from depth sensing pixels that have different asymmetrical angular responses. Each of the depth sensing pixel pairs may effectively divide the corresponding imaging lens into separate portions. Depth information for each depth sensing pixel pair may be determined based on the difference between output signals of the depth sensing pixels of that depth sensing pixel pair. The imager may be formed from various combinations of depth sensing pixel pairs and color sensing pixel pairs arranged in a Bayer pattern or other desired patterns. | 04-07-2016 |