Patent application number | Description | Published |
20080209282 | Method of managing a flash memory and the flash memory - One embodiment of the method includes determining a type of cells in a block of the flash memory if an error is detected in at least a portion of the block, and selectively changing one of a cell type indicator and a bad block indicator associated with the block based on the determined type of cells in the block. The cell type indicator indicates a type of the cells in the associated block, and the bad block indicator indicates whether the associated block is a usable block. | 08-28-2008 |
20080259686 | NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND LSB READ METHOD - A non-volatile memory device and system as well as a LSB read method are disclosed. The LSB read method includes reading LSB data from a memory cell during a main LSB read operation making reference to a flag cell threshold voltage, determining whether the LSB data contains an error, and if the LSB data contains an error re-reading the LSB data during a LSB recover-read operation without making reference to the flag cell threshold voltage. | 10-23-2008 |
20080266951 | NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD - A non-volatile memory device, related memory system, and program method for the non-volatile memory device are disclosed. In the method, memory cells in a memory cell array are accessed through a plurality of word lines by applying a program voltage to a selected word line, wherein the selected word line is not adjacent to an outmost word line, applying a first reduced pass voltage to word lines adjacent to the selected word line, and applying a second reduced pass voltage to the outermost word lines. | 10-30-2008 |
20090019215 | Method and device for performing cache reading - Method and device for reading data from a semiconductor device, where tR is a read operation time, tT is a buffer transfer time, and tH is a host transfer time, where at least two of tR, tT, and tH may be overlapped to reduce a total transfer time. | 01-15-2009 |
20100020618 | NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM - A nonvolatile memory device includes a plurality of memory cells connected to a wordline and arranged in a row direction, bitlines connected to the plurality of memory cells, respectively, and a bitline bias circuit configured to separately control bias voltages provided to the bitlines according to positions of the memory cells along the row direction. | 01-28-2010 |
20100067303 | FLASH MEMORY DEVICE CAPABLE OF REDUCED PROGRAMMING TIME - A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided. | 03-18-2010 |
20100208526 | Non-volatile memory device and method of operation therefor - In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well. | 08-19-2010 |
20110194353 | METHOD OF PROGRAMMING MEMORY CELLS FOR A NON-VOLATILE MEMORY DEVICE - A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage. | 08-11-2011 |
20110205797 | METHOD AND APPARATUS FOR PERFORMING MULTI-BLOCK ACCESS OPERATION IN NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address. | 08-25-2011 |
20120014187 | Non-volatile memory device and method of operation therefor - In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well. | 01-19-2012 |
20130238843 | METHOD AND APPARATUS FOR PERFORMING MULTI-BLOCK ACCESS OPERATION IN NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address. | 09-12-2013 |
20140211565 | METHODS OF PROGRAMMING MULTI-LEVEL CELL NONVOLATILE MEMORY DEVICES AND DEVICES SO OPERATING - To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line. | 07-31-2014 |