Patent application number | Description | Published |
20080209268 | Selective disabling of diagnostic functions within a data processing system - A data processing system | 08-28-2008 |
20080229073 | Address calculation and select-and insert instructions within data processing systems - A data processing system | 09-18-2008 |
20080250216 | Protected function calling - Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and changed and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form. The permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry, in order to assist backward compatibility. | 10-09-2008 |
20080250217 | Memory domain based security control with data processing systems - Access to memory address space is controlled by memory access control circuitry using access control data. The ability to change the access control data is controlled by domain control circuitry. Whether or not an instruction stored within a particular domain, being a set of memory addresses, is able to modify the access control data is dependent upon the domain concerned. Thus, the ability to change access control data can be restricted to instructions stored within particular defined locations within the memory address space thereby enhancing security. This capability allows systems to be provided in which call forwarding to an operating system can be enforced via call forwarding code and where trusted regions of the memory address space can be established into which a secure operating system may write data with increased confidence that that data will only be accessible by trusted software executing under control of a non-secure operating system. | 10-09-2008 |
20090112955 | Apparatus and method for performing magnitude detection of arthimetic operations - An apparatus and method is provided comprising processing circuitry, one or more registers and control circuitry. The control circuitry is configured such that it is responsive to a combined magnitude-detecting arithmetic instruction to control the processing circuitry to perform an arithmetic operation on at least one data element and further to perform a magnitude-detecting operation. The magnitude-detecting operation calculates a magnitude-indicating result providing an indication of a position of a most-significant bit of a magnitude of a result of the arithmetic operation irrespective of whether the most-significant bit position exceeds the data element width of the at least one data element. | 04-30-2009 |
20090172411 | Protecting the security of secure data sent from a central processor for processing by a further processing device - A data processing apparatus comprising: a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor in said non-secure mode, and processing data in said secure mode being performed under control of a secure operating system and processing data in said non-secure mode being performed under control of a non-secure operating system; and a further processing device for performing a task in response to a request from said data processor, said task comprising processing data at least some of which is secure data; wherein said further processing device is responsive to receipt of a signal to suspend said task to initiate: processing of said secure data using a secure key; and storage of said processed secure data to a non-secure data store; and is responsive to receipt of a signal to resume said task to initiate: retrieval of said processed secure data from said non-secure data store; and restoring of said processed secure data using said secure key; wherein said secure key is securely stored such that it is not accessible to other processes operating in said non-secure mode. | 07-02-2009 |
20090248780 | Polynomial data processing operation - A data processing system | 10-01-2009 |
20090271583 | Monitoring transactions in a data processing apparatus - Apparatus for processing data is provided comprising processing circuitry and monitoring circuitry for monitoring write transactions and performing transaction authorisations of certain transactions in dependence upon associated memory addresses. The processing circuitry is configured to enable execution of a write instruction corresponding to a write transaction to be monitored to continue to completion whilst the monitoring circuitry is performing monitoring of the write transactions and the monitoring circuitry is arranged to cause storage of write transaction data in an intermediate storage element for those transactions for which an authorisation is required. Storage of write transaction data in an intermediate storage element enables the write transaction to be reissued in dependence upon the result of the transaction authorisation although the corresponding write instruction has already completed. | 10-29-2009 |
20100217958 | Address calculation and select-and-insert instructions within data processing systems - A data processing system | 08-26-2010 |
20110185262 | ERROR MANAGEMENT - An electronic device is described which receives data from a transmitting device via a communications channel. The electronic device comprises digital processing circuitry arranged to process the data received via the communications channel to generate output data, error detection circuitry arranged to detect errors in the output data, and monitoring circuitry arranged to monitor the quality of digital processing conducted by the digital processing circuitry and generate digital performance data indicative of the monitored quality of digital processing. The electronic device also comprises control circuitry responsive to error information comprising errors detected by the error detection circuitry and the performance data generated by the monitoring circuitry to modify the operation of one or both of the transmitting device and the electronic device. The digital performance data provides the control circuitry with additional information for use in identifying where errors in signal processing are arising, enabling an informed decision be made to modify the operation of either the transmitting device or receiving device in some way, either to reduce the occurrence of errors in the output signal or to improve the speed and/or efficiency of the transmitter and/or receiver. | 07-28-2011 |
20120124421 | Error management within a data processing system - A data processing system | 05-17-2012 |
20130103972 | Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus - A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus. | 04-25-2013 |
20130132737 | CRYPTOGRAPHIC SUPPORT INSTRUCTIONS - A data processing system | 05-23-2013 |
20130283115 | DATA PROCESSING APPARATUS USING IMPLICIT DATA STORAGE AND A METHOD OF IMPLICIT DATA STORAGE - A data processing apparatus is provided having error code generation circuitry configured to generate an error code associated with a received data value, such that a bit change in the received data value can be known about by reference to the error code. Stored data values are stored in a data store and associated error codes are stored in an error code store. Error checking circuitry performs a verification operation on a stored data value and an associated error code to determine if an error has occurred in at least one of the stored data value and the associated error code during storage. The received data value comprises at least one additional bit with respect to the stored data value and the error checking circuitry is configured to reconstruct the at least one additional bit by reference to the stored data value and the associated error code. | 10-24-2013 |
20140223229 | DATA PROCESSING APPARATUS AND METHOD FOR ANALYSING TRANSIENT FAULTS OCCURRING WITHIN STORAGE ELEMENTS OF THE DATA PROCESSING APPARATUS - A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus. | 08-07-2014 |