Patent application number | Description | Published |
20080209257 | Modeller For A High-Security System - A modeller for a system for determining a residual error probability. The modeller includes a component modeller, which is adapted to receive an error probability and to model a change of the error probability due to a behaviour of a system component, in order to output a changed error probability as residual error probability. | 08-28-2008 |
20090110137 | FEEDBACK SHIFT REGISTER CONTROL - Feedback shift register control circuit including a checking circuit having an input being coupled to a seed input of a feedback shift register or to an internal node of the feedback shift register, the checking circuit configured to be responsive to a signal at the input indicating that the feedback shift register is in a not-allowed state, or is going to assume a not-allowed state to output an exception signal; and a gate circuit being coupled to the seed input or the feedback shift register and configured to be responsive to the exception signal to change the state of the feedback shift register or seed the feedback shift register such that the feedback shift register assumes an allowed state. | 04-30-2009 |
20090144351 | CONTROL OF A PSEUDO RANDOM NUMBER GENERATOR AND A CONSUMER CIRCUIT COUPLED THERETO - A system comprising a pseudo random number generator, a control circuit being configured to increase a quality of a pseudo random number output signal of the pseudo random number generator by coupling the pseudo random number generator with a true random number output signal of a true random number generator and a consumer circuit being configured to use the pseudo random number output signal before and after the increase. | 06-04-2009 |
20090172489 | CIRCUIT ARRANGEMENT AND METHOD FOR CHECKING THE FUNCTION OF A LOGIC CIRCUIT IN A CIRCUIT ARRANGEMENT - A circuit arrangement comprising a logic circuit to be tested and a test circuit is provided. The logic circuit is designed to provide output data from input data, said output data being generated from the input data by logic-circuit-internal combinations, such that the output data are in a predetermined relationship with the input data. The logic circuit is designed to detect whether the relationship is fulfilled and to provide an error signal if the relationship is not fulfilled. The test circuit is designed to alter logic-circuit-internal combinations. The test circuit is designed to detect the error signal, and is furthermore designed to output an alarm signal if the error signal is not detected upon alteration of the logic-circuit-internal combinations. | 07-02-2009 |
20090204657 | HYBRID RANDOM NUMBER GENERATOR - A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently influences the PRNG, and in the second mode the TRNG and the PRNG are connected to the output via the combinational logic. | 08-13-2009 |
20090213679 | POWER DEPENDENT MEMORY ACCESS - An apparatus and method of accessing a memory by determining available power, and accessing a number of bits of the memory in parallel, wherein the number of bits accessed in parallel is based at least in part on the available power. | 08-27-2009 |
20090319752 | ERROR DETECTION CODE MEMORY MODULE - An error detection code (EDC) memory module coupled via a bus to a data memory module. In response to a request for data words from a specified memory address within the data memory module, the data memory module provides a predetermined number of data words and the EDC memory module provides a corresponding EDC word. | 12-24-2009 |
20100182147 | REMOTE STORAGE OF DATA IN PHASE-CHANGE MEMORY - A security circuit comprising including a sensor located remotely from a central alarm handler and configured to sense an attack, and a phase-change memory cell coupled to and located remotely with the sensor, and configured to store an alarm event when the attack is sensed. | 07-22-2010 |
20100301896 | PHASE-CHANGE MEMORY SECURITY DEVICE - A semiconductor chip having a subcircuit formed in a substrate; and a phase-change memory cell located on the subcircuit, and configured to directly detect an attack on the subcircuit, or to form a shield to prevent physical access to the subcircuit. | 12-02-2010 |
20110078460 | Apparatus for Logging a Configuration of a Microprocessor System and Method for Logging a Configuration of a Microprocessor System - An apparatus includes a logging apparatus and a configuration apparatus. The logging apparatus has a security module operable to create a manipulation-proof log. The configuration apparatus is operable to configure a configurable microprocessor system. The configuration apparatus is further operable to be coupled to the logging apparatus in order to log a configuration of the microprocessor system using the logging apparatus. | 03-31-2011 |
20110254589 | INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING SAME - An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements. | 10-20-2011 |
20130176053 | INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME - An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. | 07-11-2013 |
20140045423 | ARRANGEMENT AND A METHOD FOR OPERATING AN ARRANGEMENT - An arrangement including: an electronic device including a processor; a memory; a communication interface; and a power interface; an electronic circuit including: a communication interface to communicate with the electronic device via a communication interface of the electronic device; a near field communication interface to receive signals via an electromagnetic field; a processor to be powered by the electromagnetic field, to determine an operation program code to operate the electronic device from the signals received via the electromagnetic field, and to generate at least one operation program code message including the operation program code to be transmitted to the electronic device via the communication interfaces; a power interface to transmit electrical energy to the power interface of the electronic device to enable the electronic device to at least one of store and process the at least one operation program code message. | 02-13-2014 |