Patent application number | Description | Published |
20090251201 | Multi-level anti-fuse and methods of operating and fabricating the same - Provided may be a multi-level anti-fuse and methods of fabricating and operating the same. The multi-level anti-fuse may include at least three anti-fuses having a plurality of anti-fuses connected in parallel constituting a parallel connection structure and at least one anti-fuse connected to the parallel connection structure in series, wherein the parallel connection structure may have a smaller resistance than the resistance of the anti-fuse connected in series, the plurality of anti-fuses connected in parallel may include dielectric layers having different thicknesses from one another, and the breakdown voltages of each dielectric layer may be different from one another. | 10-08-2009 |
20090267723 | Electrical fuse devices - An electrical fuse device includes a cathode and an anode formed apart from each other and a fuse link connecting the cathode and the anode. The cathode includes a first region and a second region. The second region is arranged between the first region and the fuse link. A width of the second region may be greater than a width of the first region. | 10-29-2009 |
20100007406 | Electrical fuse devices and methods of operating the same - Provided are an electrical fuse device and a method of operating the same. The electrical fuse device may include a fuse, and a driving element connected to the fuse and including a resistance change layer having a resistance that changes according to an applied voltage. The resistance change layer may have a metal-insulator transition (MIT) characteristic. As the driving element is turned on, a programming current may be applied to the fuse connected to the driving element. | 01-14-2010 |
20110156856 | Electrical fuse devices - An electrical fuse device includes a cathode and an anode formed apart from each other and a fuse link connecting the cathode and the anode. The cathode includes a first region and a second region. The second region is arranged between the first region and the fuse link. A width of the second region may be greater than a width of the first region. | 06-30-2011 |
Patent application number | Description | Published |
20120028678 | MOBILE TERMINAL AND METHOD OF CONTROLLING A THREE-DIMENSIONAL IMAGE THEREIN - A mobile terminal includes a display including a touchscreen, a plurality of cameras including a first camera and a second camera capturing a left eye image and a right eye image, respectively, to generate a three-dimensional (3D) image, and a controller for generating a 3D preview image to which at least one parameter value for one of the first camera and the second camera is set, and for displaying the generated 3D preview image on a screen of the display. | 02-02-2012 |
20120056998 | MOBILE TERMINAL AND CONTROLLING METHOD THEREOF - A mobile terminal and controlling method thereof are disclosed, by which a 3D or stereoscopic image can be generated to considerably relive an observer from visual fatigue. The present invention includes a first camera and a second camera configured to take a 3D image, a display unit displaying an image taken by at least one of the first and second cameras, and a controller controlling the first camera, the second camera and the display unit, wherein the controller sets a plurality of divisional sections on a left eye image taken by the first camera and a right eye image taken by the second camera and then generates the 3D image based on a depth value of each of a plurality of the divisional sections. | 03-08-2012 |
20130150093 | MOBILE TERMINAL AND CONTROLLING METHOD THEREOF - A mobile terminal and 3D image controlling method therein are disclosed to create a 3D image. The present invention includes displaying a map in a prescribed range on a display unit with reference to a current location, setting 1 | 06-13-2013 |
Patent application number | Description | Published |
20080209159 | MEMORY ACCESS METHOD USING THREE DIMENSIONAL ADDRESS MAPPING - A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a×b×c number of addresses of the memory accessed by the triple loop using the starting address and a function. | 08-28-2008 |
20080263281 | CACHE MEMORY SYSTEM USING TEMPORAL LOCALITY INFORMATION AND A DATA STORAGE METHOD - A cache memory system using temporal locality information and a data storage method are provided. The cache memory system including: a main cache which stores data accessed by a central processing unit; an extended cache which stores the data if the data is evicted from the main cache; and a separation cache which stores the data of the extended cache when the data of the extended cache is evicted from the extended cache and temporal locality information corresponding to the data of the extended cache satisfies a predetermined condition. | 10-23-2008 |
20090077349 | METHOD OF MANAGING INSTRUCTION CACHE AND PROCESSOR USING THE METHOD - A method of managing an instruction cache and a process of using the method are provided. The processor includes a processor core which has an active mode and an inactive mode, and an instruction cache which pre-traces a first instruction and detects a cache miss during the inactive mode, wherein the first instruction is performed by the processor core during the active mode. | 03-19-2009 |
20090077357 | Method of Power Simulation and Power Simulator - Disclosed are a method of simulating power and a power simulator. The power simulator includes a static information extracting unit that extracts static information with respect to execution of the second instruction; a dynamic information extracting unit that extracts dynamic information with respect to the execution of the second instruction; and a calculation unit that calculates an estimated power of the processor based on the static information and the dynamic information. | 03-19-2009 |
20090119456 | PROCESSOR AND MEMORY CONTROL METHOD - A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports. | 05-07-2009 |
20110219193 | PROCESSOR AND MEMORY CONTROL METHOD - A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports. | 09-08-2011 |