Patent application number | Description | Published |
20090031091 | CONTINUOUS TIMING CALIBRATED MEMORY INTERFACE - A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data. | 01-29-2009 |
20090310667 | PHASE CONTROL BLOCK FOR MANAGING MULTIPLE CLOCK DOMAINS IN SYSTEMS WITH FREQUENCY OFFSETS - A circuit for performing clock recovery according to a received digital signal ( | 12-17-2009 |
20100085123 | INJECTION-LOCKED CLOCK MULTIPLIER - Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit. In addition, on injection circuit is coupled to the oscillator. This injection circuit provides a second clock signal having a second frequency to the oscillator. Note that the second clock signal injection locks a phase and/or the first frequency of the first clock signal. Also note that a ratio of the first frequency to the second frequency is greater than or equal to one. | 04-08-2010 |
20100090732 | CLOCK AND DATA RECOVERY EMPLOYING PIECE-WISE ESTIMATION ON THE DERIVATIVE OF THE FREQUENCY - A system and method for performing clock data recovery. The system sets the phase of a recovered clock signal | 04-15-2010 |
20100102868 | Hardware and Method to Test Phase Linearity of Phase Synthesizer - A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output. | 04-29-2010 |
20100103994 | Interface With Variable Data Rate - A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined errorrate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate. | 04-29-2010 |
20100103999 | PARTIAL RESPONSE DECISION-FEEDBACK EQUALIZATION WITH ADAPTATION BASED ON EDGE SAMPLES | 04-29-2010 |
20100272215 | Signaling with Superimposed Differential-Mode and Common-Mode Signals - A data receiver circuit ( | 10-28-2010 |
20100272216 | APPARATUS AND METHODS FOR DIFFERENTIAL SIGNAL RECEIVING - A differential signal receiver | 10-28-2010 |
20100281289 | Bidirectional Memory Interface with Glitch Tolerant Bit Slice Circuits - A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation. | 11-04-2010 |
20100289544 | Receiver With Enhanced Clock And Data Recovery - A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler. | 11-18-2010 |
20110041008 | Clock Data Recovery System - A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at a second post cursor; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators. | 02-17-2011 |
20110222594 | Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices - A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. | 09-15-2011 |
20110316590 | Driver Supporting Multiple Signaling Modes - A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source thaws multiple current levels in the single-ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination. | 12-29-2011 |
20120187988 | Signal Distribution Networks and Related Methods - A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit. | 07-26-2012 |
20120192023 | Clock Data Recovery System - A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery and DFE tap adaption; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at h | 07-26-2012 |
20120218001 | Techniques for Phase Detection - A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase. | 08-30-2012 |
20120306538 | Phase Detection Circuits and Methods - A phase detector circuit compares the phases of first and second periodic input signals to generate an output signal. The phase detector includes a circuit that makes two different combinations of the first and the second periodic input signals to generate third and fourth periodic signals. This circuit causes the third periodic signal to be based on a first combination of the first periodic signal and the second periodic signal that imparts a first relative phase shift. The circuit causes the fourth periodic signal to be based on a second combination of the first periodic signal and the second periodic signal to provide a different relative phase shift. The phase detector also includes a comparison circuit that compares a measure of the power of the third periodic signal to a measure of the power of the fourth periodic signal to generate the phase comparison output signal. | 12-06-2012 |
20130136220 | Clock and Data Recovery Employing Piece-Wise Estimation on the Derivative of the Frequency - A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock. | 05-30-2013 |
20130148709 | Interface with Variable Data Rate - A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate. | 06-13-2013 |
20130195234 | Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets - A circuit for performing clock recovery according to a received digital signal | 08-01-2013 |
20140016692 | EDGE BASED PARTIAL RESPONSE EQUALIZATION - A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer. | 01-16-2014 |
20140153631 | METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES - A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. | 06-05-2014 |
20140169438 | Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing - A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery. | 06-19-2014 |
20140333356 | Signal Distribution Networks and Related Methods - A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit. | 11-13-2014 |
20140340120 | Techniques for Phase Detection - A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase. | 11-20-2014 |
20150030113 | Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets - A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals. | 01-29-2015 |
20150036732 | EDGE BASED PARTIAL RESPONSE EQUALIZATION - A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value. | 02-05-2015 |
20150078430 | HIGH-SPEED SIGNALING SYSTEMS AND METHODS WITH ADAPTABLE, CONTINUOUS-TIME EQUALIZATION - A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI. | 03-19-2015 |