Patent application number | Description | Published |
20090090973 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a device isolation insulating film which is provided in a semiconductor substrate, and an insulated-gate field-effect transistor which is disposed adjacent to the device isolation insulating film in a gate length direction, the insulated-gate field-effect transistor including a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a pair of impurity diffusion layers which are provided spaced apart in the semiconductor substrate in a manner to sandwich the gate electrode, and a redundant impurity diffusion layer which is provided between the device isolation insulating film and one of the pair of impurity diffusion layers. | 04-09-2009 |
20090279377 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array including a plurality of mutually intersecting word lines and bit lines, and a plurality of memory cells connected at intersections thereof and each having a read port and a write port provided independently; and a plurality of word line drivers operative to drive the word lines. The elements contained in the memory cell have respective sizes in common with the elements contained in the word line driver. | 11-12-2009 |
20090303777 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an aspect of the invention includes plural writing word lines; first and second writing bit lines that intersect with the writing word lines; and plural memory cells that are provided at portions in which the plural writing word lines and the first and second writing bit lines intersect with each other. In the semiconductor memory device, the memory cell includes a flip-flop circuit that includes first and second nodes of a complementary pair; a first transfer transistor that is connected between the first writing bit line and the first node, a gate of the first transfer transistor being connected to the writing word line; and a second transfer transistor that is connected between the second writing bit line and the second node, a gate of the second transfer transistor being connected to the writing word line. The first and second writing bit lines are in a floating state whenever data is not written in the memory cell. | 12-10-2009 |
20100232244 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a memory cell array including a plurality of word lines, a plurality of bit line pairs containing a first bit line and a second bit line, and a plurality of memory cells; a plurality of replica bit lines formed in the same manner as the first and second bit lines; a write buffer circuit operative to drive the first or second bit line to the ground voltage; a replica write buffer circuit operative to drive the replica bit lines to the ground voltage; and a boot strap circuit operative to drive the first or second bit line currently driven to the ground voltage further to a negative potential at a timing when the potential on the replica bit lines reaches a certain value. | 09-16-2010 |
20100302831 | SEMICONDUCTOR STORAGE DEVICE - A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line. | 12-02-2010 |
20110069574 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array, a word line driver, and a bit line booster. The memory cell array has multiple word lines WL, multiple bit line pairs BL, and multiple memory cells MC provided at the respective intersections of the word lines WL and the bit line pairs BL. The word line driver drives a selected word line WL to a positive voltage VWL when data is written to the memory cells MC. The bit line booster drives a selected bit line pair BL to a negative voltage VBL corresponding to the voltage VWL when data is written to the memory cells MC. | 03-24-2011 |
20120063210 | Semiconductor Device - Provided is a semiconductor device including an SRAM memory cell that includes: a first inverter and a second inverter that are connected to a single power-supply node and are cross-coupled to each other; a first transfer transistor; and a second transfer transistor. A predetermined voltage is applied from a voltage generation unit to a source terminal of an NMOS transistor included in the first inverter. An inversion detection unit is connected to the SRAM memory cell via the first and second transfer transistors. When a word-line selection potential is applied to a word line with the SRAM memory cell having data written therein, the inversion detection unit detects whether or not the data written in the SRAM memory cell is inverted. In accordance with the detection result of the inversion detection unit, a word-line selection-potential determination unit controls the word-line selection potential to be applied to the word line. | 03-15-2012 |
20140376319 | DELAY CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a load adjusting circuit adjusts the load of an inverter circuit based on a threshold voltage of a first conductive type transistor provided on the inverter circuit, and a driving force adjusting circuit adjusts the driving force of the inverter circuit based on the threshold voltage of the first conductive type transistor. | 12-25-2014 |
Patent application number | Description | Published |
20090279348 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array, which includes a plurality of read word lines, a plurality of first and second read bit lines, and a plurality of memory cells arranged in array. The memory cell includes a first and a second cell node in complementary pair, a first drive transistor controlled by the second cell node, and a second drive transistor controlled by the first cell node. The read word line and the first read bit line are connected with each other via the first drive transistor. The read word line and the second read bit line are connected with each other via the second drive transistor. | 11-12-2009 |
20090296497 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a logic circuit supplied with a first supply voltage; a cell array supplied with a second supply voltage higher than the first supply voltage and including plural mutually intersecting word lines and bit lines and plural memory cells connected at intersections thereof; and a word line driver operative to drive the word lines. The word line driver includes plural pull-up circuits connected between the supply terminal of the first supply voltage and the drive terminal of the word line and between the supply terminal of the second supply voltage and the drive terminal of the word line, and a pull-down circuit connected between the drive terminal of the word line and the ground terminal, and drives the word line with an intermediate voltage between the first and second supply voltages in accordance with a driving force ratio between the plural pull-up circuits at the time of driving the word line. | 12-03-2009 |
20110305073 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an aspect of the invention includes plural writing word lines; first and second writing bit lines that intersect with the writing word lines; and plural memory cells that are provided at portions in which the plural writing word lines and the first and second writing bit lines intersect with each other. In the semiconductor memory device, the memory cell includes a flip-flop circuit that includes first and second nodes of a complementary pair; a first transfer transistor that is connected between the first writing bit line and the first node, a gate of the first transfer transistor being connected to the writing word line; and a second transfer transistor that is connected between the second writing bit line and the second node, a gate of the second transfer transistor being connected to the writing word line. The first and second writing bit lines are in a floating state whenever data is not written in the memory cell. | 12-15-2011 |
20120155198 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a read bit line is driven based on data read out from a memory cell. A read port drives the read bit line based on data stored in a storage node. A read word line performs row selection via the read port at a time of reading from the memory cell. A coupling driver assists a write operation to the memory cell by controlling a potential of the storage node via the read port. | 06-21-2012 |
20120236662 | WORD-LINE-POTENTIAL CONTROL CIRCUIT - According to one embodiment, in a memory cell array, a plurality of memory cells is arranged in an array. A read circuit reads out data from the memory cells. A word line driver drives a word line of the memory cells. A characteristic control unit controls a specific characteristic of the memory cells. A word-line-potential adjusting unit adjusts a potential of the word line based on a distribution of the characteristic when the specific characteristic of the memory cells is controlled. | 09-20-2012 |
20130135948 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to an embodiment includes: a memory cell in which data is stored; a word line through which the memory cell is selected in each row; a bit line through which a signal read from the memory cell is transmitted in each column; a speed detector that detects a read speed of the memory cell; and a voltage controller that controls at least one of a voltage at the word line and a cell power supply voltage of the memory cell based on the read speed of the memory cell. | 05-30-2013 |
20130135953 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, provided are a memory cell configured to store data, a word line configured to select the memory cell in each row, a bit line configured to transfer a signal read from a memory cell in each column, a self-test circuit configured to test an operation of the memory cell, and a regulator configured to set a voltage of the word line or a cell power supply voltage of the memory cell to accelerate a disturb failure of the memory cell, based on an acceleration command from the self-test circuit. | 05-30-2013 |