Patent application number | Description | Published |
20090163013 | Method for Forming Gate of Non-Volatile Memory Device - Provided is a method for forming a gate of a non-volatile memory device. A tunneling layer, a charge trapping layer, a blocking layer, and a control gate layer are formed on a semiconductor substrate. A hard mask is formed on the control gate layer. The hard mask defines a region on which a gate is formed. A gate pattern is formed by etching the control gate layer, the blocking layer, the charge trapping layer, and the tunneling layer. A damage compensation layer on a side of the gate pattern is formed using ultra low pressure plasma of a pressure range from approximately 1 mT to approximately 100 mT. | 06-25-2009 |
20090170283 | Method of Fabricating Non-Volatile Memory Device - A method of fabricating a non-volatile memory device, A tunnel insulating layer, a floating gate, and a pad nitride layer is formed on a semiconductor substrate. A isolation region of the semiconductor substrate is formed by etching to a predetermined depth, and a liner insulating layer is formed on an entire surface of the resulting trench for device isolation. A filling insulation layer is formed on the liner insulating layer to fill the trench and a first etching process is performed on the filling insulation layer and the liner insulating layer. The surface of semiconductor is recessed by performing a second etching process on the filling insulation layer. A capping layer is formed on an entire surface of the result formed by the second etching process. The device isolation layer of a concave shape is formed by performing an etching process on the capping layer. | 07-02-2009 |
20090186456 | Method of Manufacturing Semiconductor Device using Salicide Process - A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate. | 07-23-2009 |
20130049095 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates. | 02-28-2013 |
Patent application number | Description | Published |
20080242030 | METHOD FOR MANUFACTURING FIN TRANSISTOR THAT PREVENTS ETCHING LOSS OF A SPIN-ON-GLASS INSULATION LAYER - A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region is etched so as to protrude the gate forming region in the active region. A protective layer over the semiconductor substrate is formed to fill the portion of the etched flowable insulation layer. The portion of the protective layer formed over the active region is removed to expose the active region of the semiconductor substrate. The exposed active region of the semiconductor substrate is cleaned. The protective layer remaining on the portion of the etched flowable insulation layer is removed. Gates are formed over the protruded gate forming regions in the active region. | 10-02-2008 |
20130099304 | 3-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another. | 04-25-2013 |
20130161726 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device. | 06-27-2013 |
20130168752 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers. | 07-04-2013 |
20130264629 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes. | 10-10-2013 |
20150072491 | 3-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another. | 03-12-2015 |
20150099337 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes. | 04-09-2015 |
20150099339 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device. | 04-09-2015 |
Patent application number | Description | Published |
20090047045 | IMAGE FORMING APPARATUS - An image forming apparatus capable of collecting residual toner from the donor roller by means of a plurality of magnetic rollers and consequently, reducing the occurrences of possible ghost phenomenon caused by the toner residue. The image forming apparatus includes an image receiving member having an electrostatic latent image formed on a surface thereof, a donor roller to receive a toner and form a layer of toner on an outer circumferential surface thereof, the donor roller being arranged to oppose the image receiving member so as to develop with toner the electrostatic latent image of the image receiving member, and a plurality of magnetic rollers each to support magnetic brushes of carrier. | 02-19-2009 |
20090175659 | DEVELOPING DEVICE AND IMAGE FORMING APPARATUS WITH THE SAME - A developing device to simplify a magnet of a developer delivery unit, and an image forming apparatus with the same. In the image forming apparatus comprising a photosensitive member and a developing device that includes a developing roller to supply a developer to the photosensitive member, the developing device includes a casing defining an external appearance of the developing device, a first auger section defined in the casing for agitation and conveyance of the developer, a second auger section defined in the casing and divided from the first auger section, and a developer delivery unit provided on the outside of the casing, to deliver the developer from the first auger section to the second auger section. | 07-09-2009 |
20100158573 | DEVELOPER SUPPLYING APPARATUS AND IMAGE FORMING APPARATUS HAVING THE SAME - A developer supplying apparatus can include a first chamber and a second chamber defined within a housing. Each of the first and second chambers may include an agitator disposed therein. A magnetic body may be disposed near the first chamber to receive toner from the first chamber. A controller can determine the level of developer received in the first chamber, and to based on the determined developer level control the operations of one or more of the agitators and the magnetic body in order to ensure sufficient supply of the developer in the first chamber to reduce the occurrences of image defects, such as, for example, auger marks. | 06-24-2010 |