Patent application number | Description | Published |
20090027078 | FAULT TOLERANT ASYNCHRONOUS CIRCUITS - New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits. | 01-29-2009 |
20090187395 | EVENT-SYNCHRONIZATION PROTOCOL FOR PARALLEL SIMULATION OF LARGE-SCALE WIRELESS NETWORKS - An event synchronization protocol called time-based synchronization (TBS) is employed to control operation of a network simulation. In TBS, processors in the simulated network execute events based on comparisons between timestamps for each event and a value generated by a time tracking device in the processor. In this manner, event execution is not dependent on other processes in the network and the simulation can actually be carried out at speeds faster than real time. A multiprocessor network is specially designed to execute TBS-based simulations. | 07-23-2009 |
20090201044 | LOGIC PERFORMANCE IN CYCLIC STRUCTURES - Apparatus, systems, and methods may operate to identify state holding elements and functional logic elements in an original cyclic structure, and to insert additional state holding elements or initial tokens in series with the identified functional logic elements to create a modified cyclic structure, wherein the additional state holding elements or initial tokens have substantially identical functionality to the original state holding elements. Other activities may include coupling additional functional logic elements to output nodes of the modified cyclic structure, wherein the additional functional logic elements have substantially identical functionality to the original functional logic elements. Additional apparatus, systems, and methods are disclosed. | 08-13-2009 |
20090210847 | SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION - Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed. | 08-20-2009 |
20090279346 | FAULT TOLERANT ASYNCHRONOUS CIRCUITS - New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits. | 11-12-2009 |
20090319962 | AUTOMATED CONVERSION OF SYNCHRONOUS TO ASYNCHRONOUS CIRCUIT DESIGN REPRESENTATIONS - Methods and systems for performing automated conversion of synchronous circuit design to asynchronous circuit design representations are described. A synchronous netlist may be generated from a synchronous circuit design. The synchronous netlist may include combinational logic gates and state-holding elements. The synchronous netlist may be converted to an asynchronous circuit design. The converting may include grouping the combinational logic gates by operations into functions. | 12-24-2009 |
20100005431 | CONVERTING A SYNCHRONOUS CIRCUIT DESIGN INTO AN ASYNCHRONOUS DESIGN - Methods and systems for converting synchronous circuit designs to asynchronous circuit designs are described. A method may include converting a synchronous circuit design to an asynchronous dataflow design. Functional characteristics of the synchronous circuit design may be determined. The synchronous circuit design may include multiple synchronous logic blocks and a number of connection boxes. Each synchronous logic block may be converted, based on functional characteristics, to corresponding asynchronous dataflow logic blocks. The corresponding asynchronous dataflow logic blocks may provide corresponding asynchronous dataflow logic functions that may use protocol signals. Each connection box, based on the functional characteristics, may be converted to programmable switch points and programmable switches. | 01-07-2010 |
20100013517 | RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS - In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics (302, 304) for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics. | 01-21-2010 |
20100205571 | SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION - Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed. | 08-12-2010 |
20100303067 | ASYNCHRONOUS PIPIELINED INTERCONNECT ARCHITECTURE WITH FANOUT SUPPORT - Circuits comprising an asynchronous programmable interconnect with fan out support that include a multi-port switch and a first and second buffer-switch circuit, and methods of forming such circuits, are provided. Additional circuits and methods are disclosed. | 12-02-2010 |
20110012666 | NON-PREDICATED TO PREDICATED CONVERSION OF ASYNCHRONOUS REPRESENTATIONS - Methods, circuits and systems for converting of a non-predicated asynchronous netlist to a predicated asynchronous netlist are described. These may operate to identify one or more portions of an asynchronous netlist corresponding to a partially utilized portion of an asynchronous circuit. The asynchronous netlist may be modified to control the partially utilized portion. Additional methods, circuits, and systems are disclosed. | 01-20-2011 |
20110016439 | RESET MECHANISM CONVERSION - Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed. | 01-20-2011 |
20110058570 | PROGRAMMABLE CROSSBAR STRUCTURES IN ASYNCHRONOUS SYSTEMS - Methods, systems, and circuits for forming and operating a crossbar structure in an asynchronous system are described. One or more input ports of a programmable crossbar structure may be connected to send data to one or more output ports. A group of output ports each receiving data from an input port may be connected to send, in response, control signals via a programmable element to the input port. The number of programmable elements used may be determined by the number of input ports being copied to more than one output port. Additional methods, systems, and circuits are disclosed. | 03-10-2011 |
20110062987 | ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed. | 03-17-2011 |
20110062991 | ASYNCHRONOUS CIRCUIT REPRESENTATION OF SYNCHRONOUS CIRCUIT WITH ASYNCHRONOUS INPUTS - A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input. One or more asynchronous outputs at a circuit boundary is converted to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output. | 03-17-2011 |
20110066873 | MULTI-CLOCK ASYNCHRONOUS LOGIC CIRCUITS - Methods, systems, and circuits for implementing multi-clock designs in asynchronous logic circuits are described. A method may include associating one or more data tokens with a clock domain of a multi-clock domain netlist. A durational relationship between a clock period associated with the clock domain and one or more other clock domains of the multi-clock domain netlist may be determined. Data tokens used in other clock domains may be transformed based on the determined relationship. | 03-17-2011 |
20110066986 | TOKEN ENHANCED ASYNCHRONOUS CONVERSION OF SYNCHONOUS CIRCUITS - A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and one or more additional tokens into the converted asynchronous circuit. The circuit is initialized with a desired additional number of tokens placed in the asynchronous circuit, or a desired number of tokens are inserted at an input before taking tokens from an output. | 03-17-2011 |
20110078644 | ASYCHRONOUS SYSTEM ANALYSIS - Methods, systems, and circuits that implement timing analyses of an asynchronous system are described. A method may include converting a synchronous circuit design into an asynchronous representation, wherein a critical path may be identified. The critical path may be converted to a corresponding path in the synchronous circuit design. Additional methods, systems, and circuits are disclosed. | 03-31-2011 |
20110130171 | ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed. | 06-02-2011 |
20110169524 | RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS - In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics. | 07-14-2011 |
20110298495 | ONE PHASE LOGIC - Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed. | 12-08-2011 |
20120112792 | ONE PHASE LOGIC - Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed. | 05-10-2012 |
20120119781 | RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS - In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics. | 05-17-2012 |
20120180012 | RESET MECHANISM CONVERSION - Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed. | 07-12-2012 |
20130073497 | NEUROMORPHIC EVENT-DRIVEN NEURAL COMPUTING ARCHITECTURE IN A SCALABLE NEURAL NETWORK - An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery. | 03-21-2013 |
20130099570 | SYSTEMS AND METHODS FOR ZERO-DELAY WAKEUP FOR POWER GATED ASYNCHRONOUS PIPELINES - A device including a pipeline having a number of groups of pipeline stages. Each group has at least one pipeline stage, a gated power supply power net or a gated ground power net, the gated power supply power net and the gated ground power net having components that allow gating power supply and ground to that group of pipeline stages. The device also has a number of control components, each control component controlling the gating of power supply or ground. Each group of pipeline stages controls the gating of power supply and ground of a subsequent group of pipeline stages. Each one group of pipeline stages being selected such that a forward propagation delay from a preceding group of pipeline stages to that one group is at least equal to a time required for activating gated power supply or ground in that one group. Methods of implementation are also discussed. | 04-25-2013 |
20130124592 | OPERAND-OPTIMIZED ASYNCHRONOUS FLOATING-POINT UNITS AND METHOD OF USE THEREOF - Asynchronous arithmetic units including an asynchronous IEEE 754 compliant floating-point adder and an asynchronous floating point multiplier component. Arithmetic units optimized for lower power consumption and methods for optimization are disclosed. | 05-16-2013 |
20140137064 | RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS - In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics. | 05-15-2014 |