Patent application number | Description | Published |
20080268606 | Semiconductor device manufacturing method and semiconductor device - A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided. The semiconductor device manufacturing method according to the present invention includes: a first step of forming a first electrode of a capacitor on a semiconductor substrate; a second step of forming a capacitor insulating film on the whole surface including a side surface and an upper surface of the first electrode; a third step of forming a protection insulating film made of a material different from that of the capacitor insulating film, on the capacitor insulating film; a fourth step of removing the protection insulating film and the capacitor insulating film from the upper surface of the first electrode, by anisotropically etching the protection insulating film and the capacitor insulating film; a fifth step of removing the protection insulating film that remains on the side surface of the first electrode; and a sixth step of forming a second electrode of the capacitor on the capacitor insulating film, after removing the protection insulating film. | 10-30-2008 |
20090026517 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes: a transistor including source and drain diffusion-layers, a gate insulating film and a gate electrode; first and second plugs formed in a first interlayer-insulating film and connected to the source and drain diffusion-layers, respectively; a third plug extending through a second interlayer-insulating film and connected to the first plug; a first interconnection-wire formed on the second interlayer-insulating film and connected to the third plug; a second interconnection-wire formed on a third interlayer-insulating film and intersecting the first interconnection-wire; a fourth interlayer-insulating film; a hole extending through the fourth, third and second interlayer-insulating films, the hole being formed such that a side surface of the second interconnection-wire is exposed; and a fourth plug filling the hole via an intervening dielectric film and connected to the second plug, wherein a capacitor is formed using the fourth plug, the second interconnection-wire and the dielectric film sandwiched therebetween. | 01-29-2009 |
20090087958 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof which enable to secure high yield and increase the capacity of a capacitor are provided. The semiconductor device according to the present invention includes: a plurality of capacitor layers laminated, each capacitor layer including a plurality of storage electrodes, a capacity insulating film covering the surface of the storage electrodes, and a plate electrode provided between the storage electrodes, wherein the plate electrode of each of the laminated capacitor layers are electrically connected to each other and the corresponding storage electrode of each of the laminated capacitor layers are electrically connected to each other. | 04-02-2009 |
20090121283 | Semiconductor device and fabrication method of the same - A semiconductor device includes a substrate; a first insulating layer provided on the substrate; a conductive layer buried in the first insulating layer; a semiconductor pillar including a lower diffusion layer provided immediately above the conductive layer, the lower diffusion layer being electrically connected to the conductive layer, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer; a gate insulating film provided on a peripheral side surface of the semiconductor layer; a gate electrode provided on the gate insulating film; and a second insulating layer provided such that the gate electrode and a circumference of the semiconductor pillar are buried in the second insulating layer. | 05-14-2009 |
20090200593 | SEMICONDUCTOR DEVICE HAVING MOS-TRANSISTOR FORMED ON SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device comprises MOS transistors sequentially arranged in the plane direction of a substrate, wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are implanted into a layer that is lower than a surface of the substrate in which a diffusion layer has been formed. A first device isolation area with a STI structure for separating the diffusion layers that function as a source/drain area is formed on the surface of the substrate. A second device isolation area with the STI structure for separating channel areas of the MOS transistors adjacent to each other is formed in a layer that is lower than a layer that has the first device isolation area. | 08-13-2009 |
20100001249 | Semiconductor device enabling further microfabrication - A semiconductor device includes a plurality of MOS transistors and wiring connected to a source electrode or a drain electrode of the plurality of MOS transistors and, the wiring being provided in the same layer as the source electrode and the drain electrode in a substrate, or in a position deeper than a surface of the substrate. | 01-07-2010 |
20100187698 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first wiring layer, a first interlayer insulating film over the first wiring layer, a second wiring layer crossing the first wiring layer and provided on the first interlayer insulating film, a second interlayer insulating film over the second wiring layer, and a via conductor electrically connecting the first wiring layer and the second wiring layer together. The second wiring layer includes a space separating the second wiring layer into pieces, the space being located at a position where the second wiring layer crosses the first wiring layer. The via conductor passes through the separation space such that the separated pieces of the second wiring layer are electrically connected together, the via conductor extending to the first wiring layer through the second interlayer insulating film and the first interlayer insulating film. | 07-29-2010 |
20100237397 | Semiconductor memory device and manufacturing method thereof - To provide an active region having first and second diffusion layers positioned at both sides of a gate trench and a third diffusion layer formed on a bottom surface of the gate trench, first and second memory elements connected to the first and second diffusion layers, respectively, a bit line connected to the third diffusion layer, a first gate electrode that covers a first side surface of the gate trench via a gate dielectric film and forms a channel between the first diffusion layer and the third diffusion layer, and a second gate electrode that covers a second side surface of the gate trench via a gate dielectric film and forms a channel between the second diffusion layer and the third diffusion layer. According to the present invention, because separate transistors are formed on both side surfaces of a gate trench, two times of conventional integration can be achieved. | 09-23-2010 |
20110024913 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second semiconductor chips. The first semiconductor chip includes a first engaging portion. The first engaging portion includes a first conductor. The second semiconductor chip includes a second engaging portion engaged with the first engaging portion. The second engaging portion includes a second conductor being electrically in contact with the first conductor. | 02-03-2011 |
20110104865 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device includes: a transistor including source and drain diffusion-layers, a gate insulating film and a gate electrode; first and second plugs formed in a first interlayer-insulating film and connected to the source and drain diffusion-layers, respectively; a third plug extending through a second interlayer-insulating film and connected to the first plug; a first interconnection-wire formed on the second interlayer-insulating film and connected to the third plug; a second interconnection-wire formed on a third interlayer-insulating film and intersecting the first interconnection-wire; a fourth interlayer-insulating film; a hole extending through the fourth, third and second interlayer-insulating films, the hole being formed such that a side surface of the second interconnection-wire is exposed; and a fourth plug filling the hole via an intervening dielectric film and connected to the second plug, wherein a capacitor is formed using the fourth plug, the second interconnection-wire and the dielectric film sandwiched therebetween. | 05-05-2011 |
20110284941 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device includes: a transistor including source and drain diffusion-layers, a gate insulating film and a gate electrode; first and second plugs formed in a first interlayer-insulating film and connected to the source and drain diffusion-layers, respectively; a third plug extending through a second interlayer-insulating film and connected to the first plug; a first interconnection-wire formed on the second interlayer-insulating film and connected to the third plug; a second interconnection-wire formed on a third interlayer-insulating film and intersecting the first interconnection-wire; a fourth interlayer-insulating film; a hole extending through the fourth, third and second interlayer-insulating films, the hole being formed such that a side surface of the second interconnection-wire is exposed; and a fourth plug filling the hole via an intervening dielectric film and connected to the second plug, wherein a capacitor is formed using the fourth plug, the second interconnection-wire and the dielectric film sandwiched therebetween. | 11-24-2011 |
20120012927 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a cell gate trench with a bottom face and first/second side faces; a field-shield gate trench narrower than the cell gate trench; a first upper diffusion layer between the cell gate trench and the field-shield gate trench; a second upper diffusion layer on the opposite side of the cell gate trench from the first upper diffusion layer; a third upper diffusion layer on the opposite side of the field-shield gate trench from the first upper diffusion layer; a lower diffusion layer on the bottom face of the cell gate trench; first and second storage elements electrically connected to the first and second upper diffusion layers, respectively; a bit line electrically connected to the lower diffusion layer; a word line covering first and second side faces via a gate insulating film; and a field-shield gate electrode in the field-shield gate trench via a gate insulating film. | 01-19-2012 |
20120175693 | SEMICONDUCTOR DEVICE ENABLING FURTHER MICROFABRICATION - A semiconductor device includes a plurality of MOS transistors and wiring connected to a source electrode or a drain electrode of the plurality of MOS transistors and, the wiring being provided in the same layer as the source electrode and the drain electrode in a substrate, or in a position deeper than a surface of the substrate. | 07-12-2012 |
20120241830 | SEMICONDUCTOR DEVICE HAVING CELL CAPACITORS - A semiconductor device including: a bit line being arranged on top surfaces of first and second contact plugs via a first insulation layer and extending in a direction connecting a first impurity diffusion layer and a second impurity diffusion layer; a bit line contact plug being formed through the first insulation layer and electrically connecting the bit line to the first contact plug; a first cell capacitor having a first lower electrode beside one of side surfaces of the bit line; a first insulation film insulating the bit line and the first lower electrode from each other; and a first contact conductor electrically connecting a bottom end of the first lower electrode to a side surface of the second contact plug. | 09-27-2012 |
20120248520 | SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL CELL CAPACITORS STACKED ONE ANOTHER AND MANUFACTURING METHOD THEREOF - Disclosed herein is a device that includes a semiconductor substrate having a first area, a plurality of cell transistors arranged on the first area of the semiconductor substrate, and a plurality of cell capacitors each coupled to an associated one of the cell transistors, the cell capacitors being provided so as to overlap with one another on the first area. | 10-04-2012 |
20140042431 | OXIDE SEMICONDUCTOR TARGET AND OXIDE SEMICONDUCTOR MATERIAL, AS WELL AS SEMICONDUCTOR DEVICE USING THE SAME - There are provided an oxide semiconductor material, capable of attaining stability of a threshold voltage (Vth) (threshold voltage shift amount ΔVth within a range of ±3 V in PDS and NBIS) and field-effect mobility of 5 cm | 02-13-2014 |