Patent application number | Description | Published |
20080197499 | STRUCTURE FOR METAL CAP APPLICATIONS - An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material. | 08-21-2008 |
20080224231 | TRANSISTORS HAVING V-SHAPE SOURCE/DRAIN METAL CONTACTS - A semiconductor structure. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconductor layer comprises a channel region, a first and a second source/drain regions. The channel region is disposed between the first and second source/drain regions and directly beneath and electrically insulated from the gate electrode region. The semiconductor structure further includes (d) a first and a second electrically conducting regions, and (e) a first and a second contact regions. The first electrically conducting region and the first source/drain region are in direct physical contact with each other at a first and a second common surfaces. The first and second common surfaces are not coplanar. The first contact region overlaps both the first and second common surfaces. | 09-18-2008 |
20080230868 | PATTERN ENHANCEMENT BY CRYSTALLOGRAPHIC ETCHING - A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners. | 09-25-2008 |
20080251878 | STRUCTURE INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES FOR USE IN SRAM DEVICES - Device structures embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes static random access memory (SRAM) devices. The design structure includes a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The design structure further comprises an electrically connective bridge extending across the first semiconductor region. A portion of the electrically connective bridge electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure. | 10-16-2008 |
20080251934 | Semiconductor Device Structures and Methods of Fabricating Semiconductor Device Structures for Use in SRAM Devices - Semiconductor device structures and methods of fabricating such semiconductor device structures for use in static random access memory (SRAM) devices. The semiconductor device structure comprises a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The device structure further comprises an electrically connective bridge extending across the first semiconductor region. The electrically connective bridge has a portion that electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure. | 10-16-2008 |
20080290519 | DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE - A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress. | 11-27-2008 |
20080293257 | DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE - A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress. | 11-27-2008 |
20090057780 | FINFET STRUCTURE INCLUDING MULTIPLE SEMICONDUCTOR FIN CHANNEL HEIGHTS - A semiconductor structure and a method for fabricating the semiconductor structure include a first semiconductor fin and a second semiconductor fin of the same overall height over a substrate. Due to the presence of a channel stop layer at the base of one of the first semiconductor fin and the second semiconductor fin, but not the other of the first semiconductor fin and the second semiconductor fin, the first semiconductor fin and the second semiconductor fin have different channel heights. The semiconductor fins may be used to fabricating a corresponding first finFET and a corresponding second finFET with differing performance characteristics due to the different channel heights of the first semiconductor fin and the second semiconductor fin. | 03-05-2009 |
20090090986 | FULLY AND UNIFORMLY SILICIDED GATE STRUCTURE AND METHOD FOR FORMING SAME - Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations. | 04-09-2009 |
20090186476 | STRUCTURE AND METHOD FOR IMPROVED SRAM INTERCONNECT - A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a cap layer; etching the exposed portion of the cap layer for revealing a portion of the silicon layer; etching the potion of the silicon layer, in which a portion of said silicon layer connects at least a portion of pull-down device of said SRAM to at least a portion of pull-up device of said SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. An interconnect structure is also provided. | 07-23-2009 |
20090200669 | ENHANCED INTERCONNECT STRUCTURE - The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer. | 08-13-2009 |
20090200674 | STRUCTURE AND METHOD OF FORMING TRANSITIONAL CONTACTS BETWEEN WIDE AND THIN BEOL WIRINGS - A structure and method of forming a conducting via for connecting two back end of the line (BEOL) metal wiring levels is described. The method includes forming a first interconnect structure having a first dimensional width in a first dielectric layer; depositing a second dielectric layer over said first dielectric layer; etching an interconnect trench in the said second dielectric layer; etching a interconnect via using a photo resist mask to form a first portion of the transitional via; reacting the photo resist to expand the photo resist at least in the lateral direction; etching the said dielectric layer using the reacted photo resist to form the second portion of the transitional via; and filling the said interconnect trench and the said interconnect via with metal. | 08-13-2009 |
20090236685 | EMBEDDED INTERCONNECTS, AND METHODS FOR FORMING SAME - The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition. | 09-24-2009 |
20110003473 | STRUCTURE FOR METAL CAP APPLICATIONS - An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material. | 01-06-2011 |
20110156282 | Gate Conductor Structure - A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized. | 06-30-2011 |
20110195581 | STRUCTURE AND METHOD TO ENHANCE BOTH NFET AND PFET PERFORMANCE USING DIFFERENT KINDS OF STRESSED LAYERS - In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits. | 08-11-2011 |