Patent application number | Description | Published |
20090021511 | Voltaic Level Adjusting Circuit, Method, and Display Apparatus Comprising the Same - A voltaic level adjusting circuit, a method, and a display apparatus having at least one data line are provided. The voltaic level adjusting circuit comprises a capacitor and at least one switch. The capacitor is charged to a voltaic level after receiving a reference voltage. The at least one switch is electrically connected to the at least one data line and the capacitor. A voltaic level of the at least one data line is adjusted by the voltaic level of the capacitor while the switch is turned on. | 01-22-2009 |
20100020024 | Display Apparatus and Data Read-Out Controller Thereof - A display apparatus and a data read-out controller thereof are provided. The display apparatus comprises a touch display module, a first data read-out controller, and a second data read-out controller. Each of the first and the second data read-out controllers comprises a first read-out switch, a second read-out switch, a first sampling unit, and a second sampling unit. According to the time division multiple output operated by the first sampling units, the first read-out switches, the second sampling units, and the second read-out switches of the first and the second data read-out controllers, the number of the output points and power loss can be reduced effectively. | 01-28-2010 |
20100176860 | Clocked D-type Flip Flop circuit - A clocked D-type Flip-Flop circuit has a transmission gate to admit an input data and to provide an intermediate output to a clock-controlled inverter based on the clock signals. The clock-controlled inverter is used as a latch for latching the output signal from the transmission gate and releases the latched signal by the same clock signals to an output inverter. The output of the output inverter is the Q terminal of the Flip-Flop circuit. Another output inverter is used to invert the signal from the Q terminal into a complementary output signal. In one of the embodiments of the present invention, another transmission gate is used to condition the complementary output signal. | 07-15-2010 |
20100207889 | Active pixel sensor and method for making same - A touch panel includes a plurality of active pixel sensors arranged in an array to sense a touch event. Each sensor element includes a photo-sensing element coupled to a single amplifier. The sensor element is arranged to provide a sensing voltage indicative of a light level received by the photo-sensor in a sensing period. The sensing voltage is amplified by the amplifier into an output voltage in the sensing period. Following the sensing period, the output voltage and the sensing voltage are reset to a predetermined voltage level. Following the reset period, the photo-sensor as well as the amplifier is disabled for a period so that the sensing level is caused to drop below the predetermined voltage level. | 08-19-2010 |
20110100728 | INDUCING CAPACITANCE DETECTOR AND CAPACITIVE POSITION DETECTOR OF USING SAME - One aspect of the present invention relates to an inducing capacitance detector. In one embodiment, the inducing capacitance detector has an input terminal for receiving a supply voltage; a capacitive sensor array with a first output terminal and a second output terminal; an operational amplifier having an inventing input terminal electrically connected to the first output terminal of the capacitive sensor array, a non-inventing input terminal electrically connected to the second output terminal of the capacitive sensor array and the input terminal, and an output terminal for outputting an output signal, a feedback capacitor electrically connected between the inventing input terminal and the output terminal of the operational amplifier. | 05-05-2011 |
20120038604 | Display Device Having Memory In Pixels - The present invention relates to a memory circuit integrated in each pixel of a display device includes a switching circuit and a memory unit. The switching circuit includes a first transistor having a gate configured to receive a switching control signal, a source and a drain electrically coupled to a liquid crystal capacitor of the pixel, and a second transistor having a gate configured to receive a switching control signal, a source electrically coupled to a storage capacitor of the pixel, and a drain electrically coupled to the liquid crystal capacitor. The memory unit is electrically coupled between the source of first transistor and the storage capacitor. The switching control signal is configured such that in the normal mode, the first transistor is turned off, while the second transistor is turned on, so that the storage capacitor is electrically coupled to the liquid crystal capacitor in parallel and the memory unit is bypassed, and in the still mode, the first transistor is turned on, while the second transistor is turned off, so that the storage capacitor controls the memory unit to supply a stored data to the liquid crystal capacitor. | 02-16-2012 |
Patent application number | Description | Published |
20090175405 | SHIFT REGISTER - A shift register is used for outputting an output pulse at output end in response to a delay of an input pulse received at an input end. The shift register includes a controller, a pre-charging switch, a level shifting switch, and an output generator. The controller is used for generating a level switching signal. The pre-charging switch is used for conducting a first supply voltage to a level shifting node in response to the input pulse. The level shifting switch turns on in response to the level switching signal. The output generator is used for generating the output pulse at the output end, when the level shifting switch turns on. | 07-09-2009 |
20090278586 | LEVEL SHIFT CIRCUIT - A level shift circuit for adjusting voltage level of an input signal includes a voltage dividing circuit coupled to a input terminal for outputting a first voltage signal in response to the input signal at the input terminal, and a buffer coupled to a first node for generating a second voltage signal by adjusting voltage level of the first voltage signal. The voltage dividing circuit includes a first load coupled between the first node and the first supply voltage, and a second load coupled between the input terminal and the first node. | 11-12-2009 |
20090284508 | TIME-DIVISION MULTIPLEXING SOURCE DRIVER FOR USE IN A LIQUID CRYSTAL DISPLAY DEVICE - A data driver for time-division multiplexing includes a first memory cell set having first memory cells, a second memory cell set having second memory cells, and a plurality of output lines. Each first memory cell is used for generating a first data signal in response to a first sampling control signal, and for outputting the first data signal in response to a first transmitting control signal. Each second memory cell is used for generating a second data signal in response to a second sampling control signal, and for outputting the second data signal in response to a second transmitting control signal. During a first line time period, the first sampling control signal is triggered while the second transmitting control signal is triggered. During a second line time period, the first transmitting control signal is triggered while the second sampling control signal is triggered. | 11-19-2009 |