Patent application number | Description | Published |
20080211036 | Bipolar Resistive Memory Device Having Tunneling Layer - A nonvolatile memory device includes a semiconductor substrate, a first electrode on the semiconductor substrate, a resistive layer on the first electrode, a second electrode on the resistive layer and at least one tunneling layer interposed between the resistive layer and the first electrode and/or the second electrode. The resistive layer and the tunneling layer may support transition between first and second resistance states responsive to first and second voltages applied across the first and second electrodes. The first and second voltages may have opposite polarities. | 09-04-2008 |
20090020745 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING TRANSITION METAL OXIDE LAYER AND RELATED DEVICE - Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer. | 01-22-2009 |
20090065760 | RESISTIVE MEMORY DEVICES AND METHODS OF FORMING RESISTIVE MEMORY DEVICES - Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed. | 03-12-2009 |
20090067216 | RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS - A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation. | 03-12-2009 |
20090135642 | RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS OPERATING RESPONSIVE TO READ OPERATIONS - A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block. | 05-28-2009 |
20100233849 | Methods of Forming Resistive Memory Devices - Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed. | 09-16-2010 |
20110194338 | Memory Devices Including Multi-Bit Memory Cells Having Magnetic and Resistive Memory Elements and Related Methods - An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed. | 08-11-2011 |
20110310657 | RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS OPERATING RESPONSIVE TO READ OPERATIONS - A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block. | 12-22-2011 |
20120236631 | MAGNETIC TUNNELING JUNCTION DEVICES, MEMORIES, ELECTRONIC SYSTEMS, AND MEMORY SYSTEMS, AND METHODS OF FABRICATING THE SAME - Provided is a magnetic tunneling junction device including a fixed magnetic structure; a free magnetic structure; and a tunnel barrier between the fixed magnetic structure and the free magnetic structure, at least one of the fixed magnetic structure and the free magnetic structure including a perpendicular magnetization preserving layer, a magnetic layer between the perpendicular magnetization preserving layer and the tunnel barrier, and a perpendicular magnetization inducing layer between the perpendicular magnetization preserving layer and the magnetic layer. | 09-20-2012 |
20130042081 | MAGNETIC TUNNELING JUNCTION DEVICES, MEMORIES, MEMORY SYSTEMS, AND ELECTRONIC DEVICES - Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures. | 02-14-2013 |
Patent application number | Description | Published |
20080197336 | Nonvolatile memory devices and methods of forming the same - A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen. | 08-21-2008 |
20080237693 | Storage of non-volatile memory device and method of forming the same - There is provided a storage of a non-volatile memory device and a method of forming the same. The storage of example embodiments may include a bottom electrode, a first tunneling insulating layer on the bottom electrode, a middle electrode on the first tunneling insulating layer, a second tunneling insulating layer on the middle electrode, and a top electrode on the second tunneling insulating layer. The first and second tunneling insulating layers may be formed of metal oxide having a thickness from about several Å to about several tens Å and a storage may be formed to have a width of about several tens nm. Therefore, a multi bit storage, increased integration, increased operation speed and decreased power consumption may be realized. | 10-02-2008 |
20090206427 | MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A magnetic memory device and a method of fabricating the same. The magnetic memory device includes a free layer, a write element, and a read element. The write element changes the magnetization direction of the free layer, and the read element senses the magnetization direction of the free layer. Herein, the write element includes a current confinement layer having a width smaller than the minimum width of the free layer to locally increase the density of a current flowing through the write element. | 08-20-2009 |
20100213558 | Magnetic Memory Device - A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions. | 08-26-2010 |
20110189851 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern. | 08-04-2011 |
20120135543 | Method For Forming Magnetic Tunnel Junction Structure And Method For Forming Magnetic Random Access Memory Using The Same - A method of fabricating a magnetic tunnel junction structure includes forming a magnetic tunnel junction layer on a substrate. A mask pattern is formed on a region of the second magnetic layer. A magnetic tunnel junction layer pattern and a sidewall dielectric layer pattern on at least one sidewall of the magnetic tunnel junction layer pattern are formed by performing at least one etch process and at least one oxidation process multiple times. The at least one etch process may include a first etch process to etch a portion of the magnetic tunnel junction layer using an inert gas and the mask pattern to form a first etch product. The at least one oxidation process may include a first oxidation process to oxidize the first etch product attached on an etched side of the magnetic tunnel junction layer. | 05-31-2012 |
20120292724 | MAGNETIC DEVICE - A magnetic tunnel junction element is provided. The magnetic tunnel junction element has first magnetic layer and second magnetic layer formed adjacent, e.g., on lower and upper portions of an insulating layer, respectively and each having a perpendicular magnetic anisotropy, a magnetic field adjustment layer formed on the second magnetic layer and having a perpendicular magnetic anisotropy, and a bather layer formed between the magnetic field adjustment layer and the second magnetic layer. The second magnetic layer and the magnetic field adjustment layer are magnetically decoupled from each other. | 11-22-2012 |
20130044538 | STACKED MRAM DEVICE AND MEMORY SYSTEM HAVING THE SAME - Provided is a stacked magnetic random access memory (MRAM) in which memory cell arrays having various characteristics or functions are included in memory cell layers. The stacked MRAM device includes a semiconductor substrate and at least one memory cell layers. The semiconductor substrate includes a first memory cell array. Each of the memory cell layers includes a memory cell array having a different function from the first memory cell array and is stacked on the first memory cell array. As a result, the stacked MRAM device has high density, high performance, and high reliability. | 02-21-2013 |
20140124727 | NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen. | 05-08-2014 |