Williams, Plano
Alford P. Williams, Plano, TX US
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20140149297 | AUTOMATED VALUATION MODEL WITH CUSTOMIZABLE NEIGHBORHOOD DETERMINATION - Automated valuation model with customizable neighborhood determination. A map image is displayed corresponding to a geographical area, and then user input accommodates definition of a particularly defined geographic area to provide custom identification of a neighborhood to be subject to automated valuation. Once the defined geographic area is established, the automated valuation model is applied to property data corresponding to properties within the defined geographic area. A subject property and corresponding properties within the defined geographic area are then displayed on a map image, preferably with articulation of the defined geographic area as the neighborhood of interest. The neighborhood may be defined by, among other criteria, inclusion within a user-defined shape, as well as exclusion of a user-defined shape from a displayed geographic area. | 05-29-2014 |
Byron Williams, Plano, TX US
Patent application number | Description | Published |
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20090002115 | METHOD TO IMPROVE INDUCTANCE WITH A HIGH-PERMEABILITY SLOTTED PLATE CORE IN AN INTEGRATED CIRCUIT - An inductor structure ( | 01-01-2009 |
20150041190 | HIGH VOLTAGE POLYMER DIELECTRIC CAPACITOR ISOLATION DEVICE - An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors. | 02-12-2015 |
20150044848 | HIGH VOLTAGE HYBRID POLYMERIC-CERAMIC DIELECTRIC CAPACITOR - An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer. | 02-12-2015 |
Byron L. Williams, Plano, TX US
Patent application number | Description | Published |
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20090020313 | CIRCUIT LOGIC EMBEDDED WITHIN IC PROTECTIVE LAYER - A system comprising a first layer comprising one or more metal sub-layers and a protective overcoat (PO) layer adjacent to the first layer. The PO layer is adapted to protect the first layer, and a circuit logic is at least partially embedded within the PO layer. The circuit logic couples to one of the metal sub-layers. | 01-22-2009 |
20100295149 | Integrated circuit structure with capacitor and resistor and method for forming - An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps. | 11-25-2010 |
20130302965 | METHOD FOR FORMING INTEGRATED CIRCUIT STRUCTURE WITH CAPACITOR AND RESISTOR AND METHOD FOR FORMING - An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps. | 11-14-2013 |
Byron Lovell Williams, Plano, TX US
Patent application number | Description | Published |
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20080246070 | METHODS AND APPARATUS FOR FORMING A POLYSILICON CAPACITOR - An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of polysilicon and depositing a second layer of polysilicon over the layer of dielectric. The method further includes implanting an equivalent concentration of implant in both the first layer of polysilicon into the second layer of polysilicon. | 10-09-2008 |
20090200637 | METHODS AND DEVICES FOR A HIGH-K STACKED CAPACITOR - An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit. | 08-13-2009 |
20100032801 | CAPACITOR FORMED IN INTERLEVEL DIELECTRIC LAYER - An capacitor is formed in an interlevel dielectric (ILD) layer of the integrated circuit (IC) by etching vertical trenches through the ILD and depositing conformal layers of a bottom electrode metal, a capacitor dielectric and a top electrode metal. The capacitor can attain a capacitance density of 20 nanofarads/mm | 02-11-2010 |
20100032803 | CAPACITOR CONTACT FORMED CONCURRENTLY WITH BOND PAD METALLIZATION - A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to the top electrode of the capacitor by etching small capacitor vias during a bond pad via etch process, followed by depositing and patterning bond pad metal in the capacitor vias to connect the top electrode to other circuit elements in the IC. The top electrode thickness is increased to accommodate the bond pad via etch process. | 02-11-2010 |
20110156209 | MULTIPLE ELECTRODE LAYER BACKEND STACKED CAPACITOR - In a disclosed embodiment, a stacked capacitor ( | 06-30-2011 |
20120071275 | Golf Ball - A golf ball including a plurality of continuous dynamic focus patterns between 0.5 and 8 millimeters wide on the exterior surface of the golf ball, such that each continuous dynamic focus patterns circumscribes the golf ball and the center of each said continuous dynamic focus pattern coincides with the center of said golf ball. A golf ball including at least four discrete dynamic focus patterns between 0.5 and 8 millimeters across on the exterior surface of the golf ball. A golf ball including both a plurality of continuous dynamic focus patterns and at least four discrete dynamic focus patterns on the exterior surface of the golf ball. | 03-22-2012 |
20140111301 | High-Resistance Thin-Film Resistor and Method of Forming the Resistor - The resistance of a thin-film resistor is substantially increased by forming the thin-film resistor to line one or more non-conductive trenches. By lining the one or more non-conductive trenches, the overall length of the resistor is increased while still consuming approximately the same surface area as a conventional resistor. | 04-24-2014 |
Daniel Jason Williams, Plano, TX US
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20100172494 | ENCRYPTING A PLAINTEXT MESSAGE WITH AUTHENTICAION - An encryption and authentication technique that achieves enhanced integrity verification through assured error-propagation using a multistage sequence of pseudorandom permutations. The present invention generates intermediate data-dependent cryptographic variables at each stage, which are systematically combined into feedback loops. The encryption technique also generates an authentication tag without any further steps that is N times longer than the block size where N is the number of pseudorandom permutations used in the encipherment of each block. The authentication tag provides a unique mapping to the plaintext for any number of plaintext blocks that is less than or equal to N. In addition to being a stand alone encryption algorithm, the disclosed technique is applicable to any mode that uses pseudorandom permutations such as, key dependent lookup tables, S-Boxes, and block ciphers such as RC5, TEA, and AES. | 07-08-2010 |
Phillip W. Williams, Plano, TX US
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20090146780 | UNIQUE IDENTIFICATION SYSTEM - An embodiment of the present invention includes a system and method for providing a unique and dynamic identification for members in a community. | 06-11-2009 |
20090150253 | SYSTEM AND METHOD FOR FACILITATING ADVERTISING - An embodiment of the present invention includes a system and method effectively and efficiently facilitate the selling and buying of advertising online. | 06-11-2009 |
20090254359 | SYNCHRONIZED INTERACTIVE DEMOGRAPHIC ANALYSIS - An embodiment of the present invention includes a system and method of providing synchronized interactive demographic analysis. | 10-08-2009 |
Shawn G. Williams, Plano, TX US
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20140114727 | METHOD AND SYSTEM FOR HIERARCHICAL FORECASTING - There is provided a computer-implemented method of generating a data forecasts for different levels of an entity. The method includes generating an aggregate forecast for an upper level entity comprised of two or more components. The method also includes determining mean values and a coefficient of variation for a probability distribution corresponding to future expected decomposition rates for each of the two or more components. A probability distribution parameter vector is computed based on the mean values and the coefficient of variation. The expected future decomposition rates for each of the two or more components may be computed based on the probability distribution parameter vector and a sample observation corresponding to previously observed decomposition values of each of the two or more components. Component forecasts corresponding to each of the two or more components may be computed based on the aggregate forecast and the expected future decomposition rates. | 04-24-2014 |