Patent application number | Description | Published |
20140171829 | SYSTEMS, DEVICES, AND METHODS FOR BODILY FLUID SAMPLE TRANSPORT - Bodily fluid sample transport systems, devices, and method are provided. In at least one embodiment described herein, methods are provided for the physical transport of small volumes of bodily fluid in liquid form from one location to another location. By way of nonlimiting example, the samples are collected in liquid form at a collection site, transported in liquid form, and arrive at an analysis site in liquid form. In many embodiments, the liquid form during transport is not held in a porous matrix, wicking material, webbing, or similar material that prevents sample for being extracted in liquid form at the destination site. In one embodiment, small volume of sample in each sample vessel is in the range of about 1 ml to about 1 microliter. | 06-19-2014 |
20150072362 | DEVICES, SYSTEMS, METHODS, AND KITS FOR RECEIVING A SWAB - Methods, devices, systems, and kits useful for the collection and analysis of samples obtained by swabs are disclosed. Swab containers configured for receiving a swab containing a sample; cartridges for holding one or more of: a swab container, a swab, assay units, pipette tips, vessels, transport units, and implements; systems (which may include a sample processing device); kits; and methods for their use are disclosed. A swab container may include an entry port; an assay chamber having an assay port; a conduit comprising an interior channel connecting the entry port; and an interior channel providing fluidic communication between the entry port and assay chamber. An interior channel may be configured to squeeze a portion of a swab placed in or through the conduit. A cartridge may include a cartridge frame configured to receive one or more of swab containers, assay units, transport units, pipette tips, vessels or implements. | 03-12-2015 |
20150072889 | SYSTEMS AND METHODS FOR DETECTING INFECTIOUS DISEASES - Systems, methods, and devices for detecting infections in a clinical sample are provided. Small-volume clinical samples obtained at a point-of-service (POS) location and may be tested at the POS location for multiple markers for multiple diseases, including upper and lower respiratory diseases. Samples may be tested for cytokines, or for inflammation indicators. Dilution of samples, or levels of detection, may be determined by the condition or past history of a subject. Test results may be obtained within a short amount of time after sample placement in a testing device, or within a short amount of time after being obtained from the subject. A prescription for treatment of a detected disorder may be provided, and may be filled, at the POS location. A bill may be automatically generated for the testing, or for the prescription, may be automatically sent to an insurance provider, and payment may be automatically obtained. | 03-12-2015 |
20150299777 | SYSTEMS AND METHODS FOR DETECTING INFECTIOUS DISEASES - Systems, methods, and devices for detecting infections in a clinical sample are provided. Small-volume clinical samples obtained at a point-of-service (POS) location and may be tested at the POS location for multiple markers for multiple diseases, including upper and lower respiratory diseases. Samples may be tested for cytokines, or for inflammation indicators. Dilution of samples, or levels of detection, may be determined by the condition or past history of a subject. Test results may be obtained within a short amount of time after sample placement in a testing device, or within a short amount of time after being obtained from the subject. A prescription for treatment of a detected disorder may be provided, and may be filled, at the POS location. A bill may be automatically generated for the testing, or for the prescription, may be automatically sent to an insurance provider, and payment may be automatically obtained. | 10-22-2015 |
20160070884 | SYSTEMS AND METHODS FOR DETECTING INFECTIOUS DISEASES - Systems, methods, and devices for detecting infections in a clinical sample are provided. Small-volume clinical samples obtained at a point-of-service (POS) location and may be tested at the POS location for multiple markers for multiple diseases, including upper and lower respiratory diseases. Samples may be tested for cytokines, or for inflammation indicators. Dilution of samples, or levels of detection, may be determined by the condition or past history of a subject. Test results may be obtained within a short amount of time after sample placement in a testing device, or within a short amount of time after being obtained from the subject. A prescription for treatment of a detected disorder may be provided, and may be filled, at the POS location. A bill may be automatically generated for the testing, or for the prescription, may be automatically sent to an insurance provider, and payment may be automatically obtained. | 03-10-2016 |
Patent application number | Description | Published |
20090082835 | Apparatus and Methods For Charging An Implanted Medical Device Power Source - Apparatus and methods for charging an implanted medical device. | 03-26-2009 |
20110282414 | SYSTEM AND METHOD FOR DEFINING NEUROSTIMULATION LEAD CONFIGURATIONS - A method and external control device for operating a plurality of electrode leads implanted within the tissue of a patient. A virtual electrode leads in a reference lead configuration are displayed. One of the virtual electrode leads is selected. The selected virtual electrode lead is dragged, and the displace virtual electrode lead is dropped, thereby displaying the virtual electrode leads in a new lead configuration. | 11-17-2011 |
20120012630 | CHARGER BELT - Electrical energy is transcutaneously transmitted from an external charger to an implanted medical device, wherein the external charger includes a charger head that is positioned on the patient to align with the implanted medical device for efficient charging. To secure the charger head in alignment with the implanted medical device, a belt with a buckle is provided for securing the charger head. The belt is adjustable in length by sliding end portions of the belt through a buckle and joining respective fabrics on the belt. The position of the buckle can also be adjusted for ease of patient use. Additional features of the belt provide for heat management to improve patient comfort and an additional strap to further adjust the length of the belt. | 01-19-2012 |
20120109230 | Neurostimulation system and method for graphically displaying electrode stimulation values - An external control device for use with a neurostimulation system having a neurostimulation lead carrying a plurality of electrodes capable of conveying an electrical stimulation field into tissue in which the electrodes are implanted. The external control device comprises a user interface including one or more control elements and a display screen, and a processor configured for individually assigning stimulation amplitude values for selected ones of the electrodes in response to actuations of the one or more control elements and for displaying on the display screen representations of the electrodes and a plurality of first non-alphanumeric indicators of the stimulation amplitude values in graphical association with the respective representations of the selected electrodes. | 05-03-2012 |
20120265269 | USER INTERFACE WITH VIEW FINDER FOR LOCALIZING ANATOMICAL REGION - An external control device for use with a medical component implanted within a patient. The device comprises a user interface configured for receiving user input, displaying a first graphical representation of the medical component in the context of a global graphical representation of an anatomical region of the patient, displaying a view finder defining a portion of the global graphical representation, and displaying a second graphical representation of the medical component in the context of a local graphical representation of the portion of the anatomical region portion. The external control device further comprises control circuitry configured for, in response to the input from the user, modifying the displayed view finder to spatially define a different portion of the global graphical representation, such that the second graphical representation of the medical component is displayed in the context of a local graphical representation of the different portion of the anatomical region. | 10-18-2012 |
20120290041 | NEUROSTIMULATION SYSTEM WITH ON-EFFECTOR PROGRAMMER CONTROL - An external control device for use with a programmable implantable medical device coupled to an operative element. The external control device comprises a user interface comprising a control element and a display screen configured for displaying a graphical representation of the operative element. The external control device further comprises control circuitry configured for prompting the display screen to superimpose a graphical programmer control over the graphical representation of the operative element when the control element is actuated, and modifying an operational parameter for the operative element in response to actuation of the graphical programmer control. The external control device further comprises output circuitry configured for transmitting the modified operational parameter to the programmable implantable medical device. | 11-15-2012 |
20130158628 | SEAMLESS INTEGRATION OF DIFFERENT PROGRAMMING MODES FOR A NEUROSTIMULATOR PROGRAMMING SYSTEM - A system and method for programming a neurostimulation device coupled to a plurality of electrodes implanted adjacent tissue of a patient are provided. A first electrode configuration corresponding to a first mode of programming the neurostimulation device is defined. A second programming mode of programming the neurostimulation device different from the first programming mode is selected. A second electrode configuration is defined based on the first electrode configuration in response to the selection of the second programming mode. The neurostimulation device is programmed using the second programming mode. | 06-20-2013 |
20140025140 | Self-Affixing External Charging System for an Implantable Medical Device - An external charging system for charging or powering an implantable medical device is disclosed which is self-affixing to the patient without the need for a holding device. The charging system can comprise two modules attached to opposite ends of a flexible member. The flexible member is bendable, and when bent will firmly hold its position on the patient. The two modules can comprise a coil module containing a charging coil, and an electronics module including a user interface and the necessary electronics for activating the charging coil to produce a magnetic charging field. Wires can couple the charging coil in the coil module to the electronics in the electronics modules. The entire assembly can be encased in a water proof sleeve having a high-friction surface, which protects the charging system and helps the charging system to adhere to the patient. | 01-23-2014 |
20140067015 | SYSTEM AND METHOD FOR IDENTIFYING AVAILABILITY OF CLINICIAN DEFINED PROGRAMMING SETTINGS FOR A PATIENT - An external control device for indicating whether a stimulation parameter set for use in a neurostimulator is available on a remote control in communication with the external control device is provided. The device includes a user interface configured for displaying the stimulation parameter set and an indicator that indicates whether the stimulation parameter set is available to the patient from the remote control. The device also includes control circuitry configured for, in response to input from the user (e.g., actuating the indicator), selectively turning the indicator on or off. The indicator may be an icon, and the icon may be a graphical depiction of a remote control. The user interface may be further configured for receiving additional input from the user, and the control circuitry may be further configured for, in response to the additional input from the user, programming the remote control with the stimulation parameter set. | 03-06-2014 |
20140067019 | SYSTEM AND METHOD FOR CONNECTING DEVICES TO A NEUROSTIMULATOR - A method for defining connections between a plurality of lead bodies and a plurality of output ports of a neurostimulator, and an external control device for performing the method are disclosed. The external control device includes a user interface and control circuitry. The method includes displaying the lead bodies and the output ports of the neurostimulator; selecting a first one of the lead bodies; dragging a connector from the first lead body to a first one of the output ports of the neurostimulator; and dropping the connector onto the first output port of the neurostimulator, thereby defining a connection between the first lead body and the first output port of the neurostimulator. In another embodiment, a method includes defining the connection between the first lead body and the first output port, and graphically displaying the connection between the first lead body and the first output port of the neurostimulator. | 03-06-2014 |
20140084860 | APPARATUS AND METHODS FOR CHARGING AN IMPLANTED MEDICAL DEVICE POWER SOURCE - Apparatus and methods for charging an implanted medical device. | 03-27-2014 |
20140172046 | SEAMLESS INTEGRATION OF DIFFERENT PROGRAMMING MODES FOR A NEUROSTIMULATOR PROGRAMMING SYSTEM - A system and method for programming a neurostimulation device coupled to a plurality of electrodes implanted adjacent tissue of a patient are provided. A first electrode configuration corresponding to a first mode of programming the neurostimulation device is defined. A second programming mode of programming the neurostimulation device different from the first programming mode is selected. A second electrode configuration is defined based on the first electrode configuration in response to the selection of the second programming mode. The neurostimulation device is programmed using the second programming mode. | 06-19-2014 |
20140180349 | SYSTEMS AND METHODS FOR ADJUSTING ELECTRICAL NEUROMODULATION THERAPY IN MEDICATION THERAPEUTIC WINDOW - A neuromodulation system and method for managing electrical neuromodulation therapy for a patient in conjunction with administering a pharmacological agent to the patient. Electrical energy is delivered to a target tissue region of the patient, thereby electrically modulating the target tissue region providing therapy to the patient. The energy level of the electrical energy delivered to the tissue is automatically varied inversely to the effect of the pharmacological agent on the patient during a therapeutic window. An absorption level of the pharmacological agent in the patient may be continually detected, and the energy level of the delivered electrical energy automatically varied based on the detected absorption level of the pharmacological agent during a therapeutic window. | 06-26-2014 |
20140277284 | CLINICAL RESPONSE DATA MAPPING - A system and method include a processor that, based on at least a subset of stored data of clinical effects of one or more stimulations of anatomical tissue performed using electrodes of an implanted leadwire, generates and outputs at least one graphical marking representing the at least the subset of the stored data. Each of the at least one graphical marking represents a respective portion of the at least the subset of the stored data and is output in association with a respective set of values for each of at least two parameters by which one or more the stimulations were performed. The markings are plotted in a graph defined by axes corresponding to values of respective stimulation parameters. Alternative, the markings are arranged in a column of a tabular report. The markings are two-toned to provide respective information for both therapeutic and adverse side effects. | 09-18-2014 |
20140296938 | SYSTEM AND METHOD FOR CONNECTING DEVICES TO A NEUROSTIMULATOR - A method for defining connections between a plurality of lead bodies and a plurality of output ports of a neurostimulator, and an external control device for performing the method are disclosed. The external control device includes a user interface and control circuitry. The method includes displaying the lead bodies and the output ports of the neurostimulator; selecting a first one of the lead bodies; dragging a connector from the first lead body to a first one of the output ports of the neurostimulator; and dropping the connector onto the first output port of the neurostimulator, thereby defining a connection between the first lead body and the first output port of the neurostimulator. In another embodiment, a method includes defining the connection between the first lead body and the first output port, and graphically displaying the connection between the first lead body and the first output port of the neurostimulator. | 10-02-2014 |
20150054459 | Self-Affixing External Charging System for an Implantable Medical Device - An external charging system for charging or powering an implantable medical device is disclosed which is self-affixing to the patient without the need for a holding device. The charging system can comprise a charging coil attached to a flexible member. The flexible member is bendable, and when bent will firmly hold its position on the patient. The system can include an electronics module including a user interface and the necessary electronics for activating the charging coil to produce a magnetic charging field. Wires can couple the charging coil in the coil module to the electronics in the electronics modules. The entire assembly can be encased in a water proof sleeve having a high-friction surface, which protects the charging system and helps the charging system to adhere to the patient. | 02-26-2015 |
20150073503 | SYSTEM AND METHOD FOR CONNECTING DEVICES TO A NEUROSTIMULATOR - A method for defining connections between a plurality of lead bodies and a plurality of output ports of a neurostimulator, and an external control device for performing the method are disclosed. The external control device includes a user interface and control circuitry. The method includes displaying the lead bodies and the output ports of the neurostimulator; selecting a first one of the lead bodies; dragging a connector from the first lead body to a first one of the output ports of the neurostimulator; and dropping the connector onto the first output port of the neurostimulator, thereby defining a connection between the first lead body and the first output port of the neurostimulator. In another embodiment, a method includes defining the connection between the first lead body and the first output port, and graphically displaying the connection between the first lead body and the first output port of the neurostimulator. | 03-12-2015 |
20150073504 | SEAMLESS INTEGRATION OF DIFFERENT PROGRAMMING MODES FOR A NEUROSTIMULATOR PROGRAMMING SYSTEM - A system and method for programming a neurostimulation device coupled to a plurality of electrodes implanted adjacent tissue of a patient are provided. A first electrode configuration corresponding to a first mode of programming the neurostimulation device is defined. A second programming mode of programming the neurostimulation device different from the first programming mode is selected. A second electrode configuration is defined based on the first electrode configuration in response to the selection of the second programming mode. The neurostimulation device is programmed using the second programming mode. | 03-12-2015 |
20160082266 | SYSTEM AND METHOD FOR CONNECTING DEVICES TO A NEUROSTIMULATOR - A method for defining connections between a plurality of lead bodies and a plurality of output ports of a neurostimulator, and an external control device for performing the method are disclosed. The external control device includes a user interface and control circuitry. The method includes displaying the lead bodies and the output ports of the neurostimulator; selecting a first one of the lead bodies; dragging a connector from the first lead body to a first one of the output ports of the neurostimulator; and dropping the connector onto the first output port of the neurostimulator, thereby defining a connection between the first lead body and the first output port of the neurostimulator. In another embodiment, a method includes defining the connection between the first lead body and the first output port, and graphically displaying the connection between the first lead body and the first output port of the neurostimulator. | 03-24-2016 |
20160082267 | SEAMLESS INTEGRATION OF DIFFERENT PROGRAMMING MODES FOR A NEUROSTIMULATOR PROGRAMMING SYSTEM - A system and method for programming a neurostimulation device coupled to a plurality of electrodes implanted adjacent tissue of a patient are provided. A first electrode configuration corresponding to a first mode of programming the neurostimulation device is defined. A second programming mode of programming the neurostimulation device different from the first programming mode is selected. A second electrode configuration is defined based on the first electrode configuration in response to the selection of the second programming mode. The neurostimulation device is programmed using the second programming mode. | 03-24-2016 |
20160101291 | APPARATUS AND METHODS FOR CHARGING AN IMPLANTED MEDICAL DEVICE POWER SOURCE - Apparatus and methods for charging an implanted medical device. | 04-14-2016 |
Patent application number | Description | Published |
20100295152 | Precision high-frequency capacitor formed on semiconductor substrate - A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique. | 11-25-2010 |
20110042742 | STRUCTURES OF AND METHODS OF FABRICATING TRENCH-GATED MIS DEVICES - In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs. | 02-24-2011 |
20110049580 | Hybrid Packaged Gate Controlled Semiconductor Switching Device Using GaN MESFET - A hybrid packaged gate controlled semiconductor switching device (HPSD) has an insulated-gate transistor (IGT) made of a first semiconductor die and a rectifying-gate transistor (RGT) made of a second semiconductor die. The RGT gate and source are electrically connected to the IGT source and drain respectively. The HPSD includes a package base with package terminals for interconnecting the HPSD to external environment. The IGT is die bonded atop the package base. The second semiconductor die is formed upon a composite semiconductor epi layer overlaying an electrically insulating substrate (EIS) thus creating a RGT die. The RGT die is stacked and bonded atop the IGT die via the EIS. The IGT, RGT die and package terminals are interconnected with bonding wires. Thus, the HPSD is a stacked package of IGT die and RGT die with reduced package footprint while allowing flexible placements of device terminal electrodes on the IGT. | 03-03-2011 |
20110176247 | PRECISION HIGH-FREQUENCY CAPACITOR FORMED ON SEMICONDUCTOR SUBSTRATE - A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique. | 07-21-2011 |
20110233666 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process. | 09-29-2011 |
20110233667 | DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH AND THREE OR FOUR MASKS PROCESS - A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device. | 09-29-2011 |
20120074896 | Semiconductor Device Die with Integrated MOSFET and Low Forward Voltage Diode-Connected Enhancement Mode JFET and Method - A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode. | 03-29-2012 |
20120132988 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process. | 05-31-2012 |
20120146090 | SELF ALIGNED TRENCH MOSFET WITH INTEGRATED DIODE - Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact. | 06-14-2012 |
20120193676 | Diode structures with controlled injection efficiency for fast switching - This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer. | 08-02-2012 |
20120199875 | CASCODE SCHEME FOR IMPROVED DEVICE SWITCHING BEHAVIOR - A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes. | 08-09-2012 |
20120248530 | APPROACH TO INTERGRATE SCHOTTKY IN MOSFET - An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions. | 10-04-2012 |
20120329225 | POWER MOS DEVICE FABRICATION - Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug. | 12-27-2012 |
20130043527 | SHIELDED GATE TRENCH MOSFET PACKAGE - A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element can be electrically connected between the shield electrode pad and the source lead in the package. | 02-21-2013 |
20130105886 | TWO-DIMENSIONAL SHIELDED GATE TRANSISTOR DEVICE AND METHOD OF MANUFACTURE | 05-02-2013 |
20130126966 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process. | 05-23-2013 |
20130175612 | DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH - A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device. | 07-11-2013 |
20130224919 | METHOD FOR MAKING GATE-OXIDE WITH STEP-GRADED THICKNESS IN TRENCHED DMOS DEVICE FOR REDUCED GATE-TO-DRAIN CAPACITANCE - A method for making gate-oxide with step-graded thickness (S-G GOX) in a trenched DMOS device is proposed. First, a substrate is provided and a silicon oxide-silicon nitride-silicon oxide (ONO) protective composite layer is formed atop. Second, an upper interim trench (UIT), an upper trench protection wall (UTPW) and a lower interim trench (LIT) are created into the substrate. Third, the substrate material surrounding the LIT is shaped and oxidized into a desired thick-oxide-layer of thickness T | 08-29-2013 |
20140048846 | SELF ALIGNED TRENCH MOSFET WITH INTEGRATED DIODE - Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact. | 02-20-2014 |
20140138767 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process. | 05-22-2014 |
20140151790 | APPROACH TO INTEGRATE SCHOTTKY IN MOSFET - An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions. | 06-05-2014 |
20140175540 | HIGH FREQUENCY SWITCHING MOSFETS WITH LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD - Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 06-26-2014 |
20140239382 | HIGH FREQUENCY SWITCHING MOSFETS WITH LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD - Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 08-28-2014 |
20140252494 | INTEGRATED SNUBBER IN A SINGLE POLY MOSFET - Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 09-11-2014 |
20140264571 | SHIELDED GATE TRENCH MOSFET PACKAGE - A trench formed in a body layer and epitaxial layer of a substrate is lined with a dielectric layer. A shield electrode formed within a lower portion of the trench is insulated by the dielectric layer. A gate electrode formed in the trench above the shield electrode is insulated from the shield electrode by another dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element is electrically connected between the shield electrode pad and a source lead. | 09-18-2014 |
20140339630 | DEVICE STRUCTURE AND METHODS OF MAKING HIGH DENSITY MOSFETS FOR LOAD SWITCH AND DC-DC APPLICATIONS - Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 11-20-2014 |
20150060936 | PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS - This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate. | 03-05-2015 |
20150097232 | DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH - A semiconductor device has a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the semiconductor substrate and electrically connected to the gate electrodes. The first gate runner abuts and surrounds the active region. A second gate runner is connected to the first gate runner to make contact to a gate metal. A dielectric filled trench surrounds the first and second gate runners and the active region and a highly doped channel stop region is formed under the dielectric filled trench. | 04-09-2015 |
20150129956 | METHOD TO MANUFACTURE SHORT CHANNEL TRENCH MOSFET - Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 05-14-2015 |
20150137225 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process. | 05-21-2015 |
20150137227 | HIGH FREQUENCY SWITCHING MOSFETS WITH LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD - Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 05-21-2015 |
20150145037 | HIGH DENSITY TRENCH-BASED POWER MOSFETS WITH SELF-ALIGNED ACTIVE CONTACTS AND METHOD FOR MAKING SUCH DEVICES - Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T | 05-28-2015 |
20150162777 | Battery Charging Circuit with Serial Connection of MOSFET and An Enhancement Mode JFET Configured as Reverse Blocking Diode with Low Forward Voltage Drop - A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode. | 06-11-2015 |
20150311295 | SPLIT POLY CONNECTION VIA THROUGH-POLY-CONTACT (TPC) IN SPLIT-GATE BASED POWER MOSFETS - Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 10-29-2015 |
20150372133 | METHOD TO MANUFACTURE SHORT CHANNEL TRENCH MOSFET - Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 12-24-2015 |
20150380544 | DEVICE STRUCTURE AND METHODS OF MAKING HIGH DENSITY MOSFETS FOR LOAD SWITCH AND DC-DC APPLICATIONS - Aspects of the present disclosure describe a high density trench-based power. The active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. A lightly doped sub-body layer may be formed below a body region between two or more adjacent active device structures of the plurality. The sub-body layer extends from a depth of the upper portion of the gate oxide to a depth of the lower portion of the gate oxide It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 12-31-2015 |
20160064551 | HIGH DENSITY TRENCH-BASED POWER MOSFETS WITH SELF-ALIGNED ACTIVE CONTACTS AND METHOD FOR MAKING SUCH DEVICES - Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 03-03-2016 |
20160099308 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. | 04-07-2016 |
20160118380 | INTEGRATED SNUBBER IN A SINGLE POLY MOSFET - Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events. | 04-28-2016 |