Patent application number | Description | Published |
20080197425 | Semiconductor device - A semiconductor device has a trench isolation structure and a high voltage circuit section including at least one well region, a MOS transistor, and an interconnect for electrically connecting elements. An electrode for preventing inversion layer formation is formed in a region above the trench isolation region provided near an end portion of the well region and below the interconnect for preventing parasitic formation of an inversion layer on a surface of the semiconductor substrate due to the potential of the interconnect, and fixed at the same potential as that of the semiconductor substrate therebelow. Further, a guard ring region formed of a heavily doped impurity region of the same conductivity type as the semiconductor substrate is provided below the electrode for preventing inversion layer formation and is fixed at the same potential as that of the semiconductor substrate to capture carriers to prevent latch-up. | 08-21-2008 |
20090039431 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device, including: an N-type MOS transistor for an internal element and a P-type MOS transistor for an internal element both provided in an internal circuit region; and an N-type MOS transistor for ESD protection provided between an external connection terminal and the internal circuit region, in which a gate electrode of the N-type MOS transistor for ESD protection is formed of P-type polysilicon. | 02-12-2009 |
20090050966 | SEMICONDUCTOR DEVICE - In order to suppress an off leak current of an off transistor for ESD protection, in an NMOS for ESD protection whose isolation region has a shallow trench structure, a drain region is placed apart from the shallow trench isolation region so as not to be in direct contact with the shallow trench isolation region in a region where the drain region of the NMOS transistor for ESD protection is adjacent to at least a gate electrode of the NMOS transistor for ESD protection. | 02-26-2009 |
20090050967 | SEMICONDUCTOR DEVICE - In a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection surrounded by a shallow trench for device isolation, in order to suppress the off-leak current in an off state, there is formed, in the vicinity of the drain region of the NMOS transistor for ESD protection, an n-type region receiving a signal from an external connection terminal via a p-type region in contact with the drain region of the NMOS transistor for ESD protection. | 02-26-2009 |
20090050968 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger. | 02-26-2009 |
20090050969 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element. | 02-26-2009 |
20090101973 | Field effect transistor formed on an insulating substrate and integrated circuit thereof - A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation. | 04-23-2009 |
20090121223 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips. | 05-14-2009 |
20090152633 | Semiconductor device - In a semiconductor device including, between an external connection terminal and an internal circuit region, an NMOS transistor for ESD protection having a gate potential fixed to a ground potential, the external connection terminal is formed above a drain region of the NMOS transistor for ESD protection, and the drain region is surrounded by a source region through a channel region. Further, the drain region has a shape with rounded corners in plan view. | 06-18-2009 |
20110073947 | Semiconductor device - Provided is a semiconductor device in which the first trench isolation regions is placed between a substrate potential-fixing P-type diffusion region of an ESD protection NMOS transistor and source and drain regions of the ESD protection NMOS transistor, and has a depth greater than a depth of the second trench isolation region that is placed between a substrate potential-fixing P-type diffusion region of an NMOS transistor for internal circuit and source and drain regions of the NMOS transistor for internal circuit. | 03-31-2011 |
20110073948 | Semiconductor device - Provided is a semiconductor device including an ESD protection N-MOS transistor isolated from another element by a shallow trench structure, in which the ESD protection N-MOS transistor includes a drain region on which a thin insulating film is formed, and an electrode which receives a signal from an external connection terminal is formed on the thin insulating film. | 03-31-2011 |
20110163384 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which the drain region of the ESD protection NMOS transistor is electrically connected, through a drain extension region formed by an impurity diffusion region having the same conductivity as that of the drain region and arranged on both side surfaces and a bottom surface of the second trench isolation region which is formed next to the drain region, to the drain contact region formed by an impurity diffusion region having the same conductivity as that of the drain region. | 07-07-2011 |
20110278686 | Semiconductor device and method of manufacturing semiconductor device - Provided is a semiconductor device for performing photoelectric conversion of incident light, including: a p-type substrate ( | 11-17-2011 |
20120153375 | Nonvolatile semiconductor memory device - Provided is an electrically erasable and programmable nonvolatile semiconductor memory device whose tunnel region formed in the drain region has the second conductivity-type low-impurity-concentration region with the first tunnel insulating film for solely injecting electrons disposed thereon, and the first conductivity-type low-impurity-concentration region with the second tunnel insulating film for solely ejecting electrons disposed thereon, both regions fixed to the same potential as the drain region and having a lower impurity concentration than that of the drain region. | 06-21-2012 |
20120161272 | IMAGE SENSOR IC - In a manufacturing method for an image sensor integrated circuit, a plurality of pixel regions each having a photodiode are arranged on a silicon substrate. A light-transmissive conductive film is formed over the silicon substrate. A protective film is formed on the light-transmissive conductive film while holding a potential of the light-transmissive conductive film at the same potential as that of the silicon substrate. | 06-28-2012 |
20120168844 | Nonvolatile semiconductor memory device - Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a tunnel region; the tunnel region and the peripheral of the tunnel region are dug down to be made lower, and a depletion electrode, to which an arbitral potential is given to deplete a part of the tunnel region through a depletion electrode insulating film, is arranged in the lowered drain region. | 07-05-2012 |
20120168845 | Nonvolatile semiconductor memory device - Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a small hole in a second conductivity-type drain region, a tunnel insulating film formed on the surface of the hole, and a protrusion extended from the floating gate electrode and arranged to fill the hole. Further a tunneling restriction region which is an electrically floating first conductivity type region arranged in a vicinity of the surface of the drain region around the hole to define the size of the tunnel region through which the tunnel current flows. | 07-05-2012 |