Patent application number | Description | Published |
20120283288 | 1-(5-TERT-BUTYL-2-PHENYL-2H-PYRAZOL-3-YL)-3-[2-FLUORO-4-(1-METHYL-2-OXO-2,- 3-DIHYDRO-1H-IMIDAZO[4,5-B]PYRIDIN-7-YLOXY)-PHENYL]-UREA AND RELATED COMPOUNDS AND THEIR USE IN THERAPY - The present invention pertains generally to the field of therapeutic compounds, and more specifically to certain compounds of the following formula (I) (for convenience, collectively referred to herein as “IP compounds”), which, inter alia, are useful in the treatment of cancer, e.g., cancer characterised by (e.g., driven by) mutant RAS (“mutant RAS cancer”). The present invention also pertains to pharmaceutical compositions comprising such compounds, and the use of such compounds and compositions in the treatment of cancer, e.g., mutant RAS cancer. | 11-08-2012 |
20140357663 | 1-(5-TERT-BUTYL-2-PHENYL-2H-PYRAZOL-3-YL)-3-[2-FLUORO-4-(1-METHYL-2-OXO-2,- 3-DIHYDRO-1H-IMIDAZO[4,5-B]PYRIDIN-7-YLOXY)-PHENYL]-UREAAND RELATED COMPOUNDS AND THEIR USE IN THERAPY - The present invention pertains generally to the field of therapeutic compounds, and more specifically to certain compounds of the following formula (for convenience, collectively referred to herein as “IP compounds”), which, inter alia, are useful in the treatment of cancer, e.g., cancer characterised by (e.g., driven by) mutant RAS (“mutant RAS cancer”). The present invention also pertains to pharmaceutical compositions comprising such compounds, and the use of such compounds and compositions in the treatment of cancer, e.g., mutant RAS cancer. | 12-04-2014 |
Patent application number | Description | Published |
20130153277 | ELECTRICALLY BONDED ARRAYS OF TRANSFER PRINTED ACTIVE COMPONENTS - An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed. | 06-20-2013 |
20130215929 | INDIRECT TEMPERATURE MEASUREMENTS OF DIRECT BANDGAP (MULTIJUNCTION) SOLAR CELLS USING WAVELENGTH SHIFTS OF SUB-JUNCTION LUMINESCENCE EMISSION PEAKS - Methods and structures may be used to measure operating temperatures of isolated cells and/or fully interconnected cells inside a Concentrator Photovoltaic (CPV) module. The method may use spectrometers to measure wavelength shifts of a sub-cell electro-luminescence and/or photo-luminescence emission spectrum. A sub-cells' intrinsic bandgap temperature-dependence relations may be used to indirectly compute the operating temperature of each subcell. A sub-cells' intrinsic bandgap temperature-dependence coefficients can be measured by performing quantum efficiency measurements and/or by recording the electro-luminescence and/or photo-luminescence emission profile of a solar cell at multiple temperatures. | 08-22-2013 |
20130273695 | SELECTIVE TRANSFER OF ACTIVE COMPONENTS - A method for selectively transferring active components ( | 10-17-2013 |
20140261628 | HIGH EFFICIENCY SOLAR RECEIVERS INCLUDING STACKED SOLAR CELLS FOR CONCENTRATOR PHOTOVOLTAICS - A solar receiver includes at least two electrically independent photovoltaic cells which are stacked. An inter-cell interface between the photovoltaic cells includes a multi-layer dielectric stack. The multi-layer dielectric stack includes at least two dielectric layers having different refractive indices. Related devices and fabrication methods are also discussed. | 09-18-2014 |
20150079783 | Methods of Forming Printable Integrated Circuit Devices and Devices Formed Thereby - Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer. | 03-19-2015 |
20150327388 | Electrically Bonded Arrays of Transfer Printed Active Components - An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed. | 11-12-2015 |
20150380619 | STRUCTURES AND METHODS FOR TESTING PRINTABLE INTEGRATED CIRCUITS - A substrate includes an anchor area physically secured to a surface of the substrate and at least one printable electronic component. The at least one printable electronic component includes an active layer having one or more active elements thereon, and is suspended over the surface of the substrate by electrically conductive breakable tethers. The electrically conductive breakable tethers include an insulating layer and a conductive layer thereon that physically secure and electrically connect the at least one printable electronic component to the anchor area, and are configured to be preferentially fractured responsive to pressure applied thereto. Related methods of fabrication and testing are also discussed. | 12-31-2015 |
Patent application number | Description | Published |
20130182333 | APPARATUS AND PROCESS FOR PRODUCING PLANO-CONVEX SILICONE-ON-GLASS LENS ARRAYS - Coating a machined mold with a flowable, hardenable polymer coating produces an optically-smooth finish and maintains sharpness in upward-pointing features. These procedures produce molds for highly efficient plano-convex silicone-on-glass lens arrays in a fast and inexpensive manner in which an end-mill defines the shape of a lens, and the coating produces its smoothness. End-mill machining and coating lens-shaped features in plates that have movable pins produce molds with eject features disposed inside features that form templates for lens elements without significantly reducing optical performance. Additionally, machining and coating plates that have movable inserts produce molds for lens arrays with reduced volume and one or several rings in each lens element. | 07-18-2013 |
20130196474 | MATERIALS AND PROCESSES FOR RELEASING PRINTABLE COMPOUND SEMICONDUCTOR DEVICES - A method of fabricating transferable semiconductor devices includes providing a release layer including indium aluminum phosphide on a substrate, and providing a support layer on the release layer. The support layer and the substrate include respective materials, such as arsenide-based materials, such that the release layer has an etching selectivity relative to the support layer and the substrate. At least one device layer is provided on the support layer. The release layer is selectively etched without substantially etching the support layer and the substrate. Related structures and methods are also discussed. | 08-01-2013 |
20130221355 | STRUCTURES AND METHODS FOR TESTING PRINTABLE INTEGRATED CIRCUITS - A substrate includes an anchor area ( | 08-29-2013 |
20140191236 | Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations. | 07-10-2014 |
20150372636 | Tracking Photovoltaic Solar System, and Methods for Installing or for Using Such Tracking Photovoltaic Solar System - A tracking photovoltaic solar system, and methods for installing or for using such tracking comprising at least a dual axis tracker unit maintaining an array of photovoltaic modules aligned to the sun. Said tracker unit includes: a pair of sub-frames supporting photovoltaic modules, a torque tube supporting said subframes rotating around a primary rotation axis, a pole structure fixed and extending vertically above an anchoring basis and being rotatively connected to said longitudinal support, secondary rotating means controlling the orientation of said sub-frames around corresponding secondary rotation axis of said sub-frames, said secondary rotation axis being orthogonal to said primary rotation axis and actuators means for controlling said primary and secondary rotating means. The secondary rotation axis are located at each end of said torque tube, said pole structure being central with regard to said sub-frames and said actuators means of both primary and secondary rotating means are linear. | 12-24-2015 |
Patent application number | Description | Published |
20140028278 | DUAL REGULATOR SYSTEMS - A microcontroller system includes a main voltage regulator and a low power voltage regulator having a static current consumption less than the static current consumption of the main voltage regulator. A power state controller enables the low power voltage regulator during a power saving mode. On exiting the power saving mode, the power state controller enables the main voltage regulator and disables the low power voltage regulator after determining that the main voltage regulator is ready. The switching circuitry can be asynchronous. | 01-30-2014 |
20140028384 | REFERENCE VOLTAGE CIRCUITS IN MICROCONTROLLER SYSTEMS - A microcontroller system includes a higher power reference voltage circuit and a lower power reference voltage circuit configured to draw less power than the higher power reference voltage circuit when enabled. The system includes a power state logic controller configured to enable the lower power reference voltage circuit to provide a first regulated voltage during a power saving mode, and, on exiting the power saving mode, enable the higher power reference voltage circuit to provide a second regulated voltage. | 01-30-2014 |
20140075066 | LOW-POWER MODES OF MICROCONTROLLER OPERATION WITH ACCESS TO CONFIGURABLE INPUT/OUTPUT CONNECTORS - A microcontroller includes I/O pins whose respective functions are configurable by an I/O controller in accordance with user-programmable input. The availability of such configurable I/O pins is extended to low-power or power savings modes of operation during which the I/O controller is powered off or deactivated. | 03-13-2014 |
20140075231 | MICROCONTROLLER INPUT/OUTPUT CONNECTOR STATE RETENTION IN LOW-POWER MODES - A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode. | 03-13-2014 |
20140089706 | DELAYING RESET SIGNALS IN A MICROCONTROLLER SYSTEM - A microcontroller system includes a reset delaying module that is configured to, during a power saving mode, receive and delay a reset signal from a reset source. The reset delaying module waits for a regulator ready signal from a voltage regulator because, prior to the reset signal, the voltage regulator is in a power saving mode. In response to receiving the regulator ready signal, the reset delaying module releases the reset, e.g., to a reset controller. | 03-27-2014 |
20140089707 | CHANGING POWER MODES OF A MICROCONTROLLER SYSTEM - A microcontroller system can operate in a number of power modes. In response to changing from a previous mode to a present mode, the microcontroller system reads a present calibration value correspond to the present mode from system configuration storage and write the present calibration value to a configuration register for a component. A logic block for the component reads the present calibration value and calibrates the component. | 03-27-2014 |
20140089708 | DELAYING INTERRUPTS IN A MICROCONTROLLER SYSTEM - A microcontroller system includes a power manager that is configured to, during a power saving mode, configure an interrupt delaying module to receive and hold an interrupt from an interrupt source. In response to receiving the interrupt from the interrupt source, the power manager causes the microcontroller system to exit the power saving mode. Upon exiting the power saving mode, the power manager configures the interrupt delaying module to release the interrupt. | 03-27-2014 |
20140089714 | CONFIGURING POWER DOMAINS OF A MICROCONTROLLER SYSTEM - A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain in response to event from an event generating module without activating a processor of the microcontroller system. | 03-27-2014 |
20140266333 | GENERATING CLOCK ON DEMAND - A clock generation system for an integrated circuit (IC) chip (e.g., a microcontroller) is disclosed that allows digital blocks and other components in the IC chip to start and stop internal clocks dynamically on demand to reduce power consumption. | 09-18-2014 |
20150095681 | CONFIGURING POWER DOMAINS OF A MICROCONTROLLER SYSTEM - A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain based on whether the microcontroller system has asserted a power trigger for any module in the power domain or if any module in the power domain has asserted a power keeper. | 04-02-2015 |
20150253839 | MICROCONTROLLER INPUT/OUTPUT CONNECTOR STATE RETENTION IN LOW-POWER MODES - A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode. | 09-10-2015 |
Patent application number | Description | Published |
20090015315 | CIRCUIT FOR CONTROLLING AN A.C. SWITCH - A circuit for generating a D.C. signal for controlling an A.C. switch referenced to a first potential, from a high-frequency signal referenced to a second potential, including: a first capacitive element connecting a first input terminal, intended to receive the high-frequency signal, to the cathode of a rectifying element having its anode connected to a first output terminal intended to be connected to a control terminal of the switch; and a second capacitive element connecting a second input terminal, intended to be connected to the second reference potential, to a second output terminal intended to be connected to the first reference potential, a second rectifying element connecting the cathode of the first rectifying element to the second output terminal. | 01-15-2009 |
20110210372 | HIGH-VOLTAGE VERTICAL POWER COMPONENT - A high-voltage vertical power component including a lightly-doped semiconductor substrate of a first conductivity type and, on the side of an upper surface, an upper semiconductor layer of the second conductivity type which does not extend all the way to the component periphery, wherein the component periphery includes, on the lower surface side, a ring-shaped diffused region of the second conductivity type extending across from one third to half of the component thickness; and on the upper surface side, an insulated ring-shaped groove crossing the substrate to penetrate into an upper portion of ring-shaped region. | 09-01-2011 |
20110284921 | HF-CONTROLLED BIDIRECTIONAL SWITCH - A bidirectional switch controllable by a voltage between its gate and rear electrode and including an N-type semiconductor substrate surrounded with a P-type well; on the front surface side, a P-type well in which is formed a first N-type region; on the rear surface side, a P-type layer in which is formed a second N-type region. The well is doped to less than 10 | 11-24-2011 |
20120012891 | VOLTAGE-CONTROLLED BIDIRECTIONAL SWITCH - A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch. | 01-19-2012 |
20120061719 | SHOCKLEY DIODE HAVING A LOW TURN-ON VOLTAGE - A Shockley diode including: a vertical stack of first to fourth layers of alternated conductivity types between first and second electrodes; a recess formed in the fourth layer and extending vertically to penetrate into the second layer; a first region of same conductivity type as the second layer but of greater doping level, extending at the bottom of the recess in the second layer; and a second region of same conductivity type as the third layer but of greater doping level, extending along the lateral walls of the recess and connecting the first region to the fourth layer. | 03-15-2012 |
20120146089 | FOUR-QUADRANT TRIAC - A vertical four-quadrant triac wherein the gate region, arranged on the side of a front surface, includes a U-shaped region of a first conductivity type, the base of the U lying against one side of the structure, the main front surface region of the second conductivity type extending in front of the gate region and being surrounded with portions of the main front surface region of the first conductivity type. | 06-14-2012 |
20120161198 | BIDIRECTIONAL SHOCKLEY DIODE WITH EXTENDED MESA - A mesa-type bidirectional Shockley diode including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of said regions of the first conductivity type, each buried region being complementary in projection with the other; and a groove arranged in the vicinity of the periphery of the component on each of its surfaces, the component portion external to the groove comprising, under the external portion of the upper and lower regions of the second conductivity type, regions of the first conductivity type of same doping profile as said buried regions. | 06-28-2012 |
20120161199 | MESA-TYPE BIDIRECTIONAL SHOCKLEY DIODE - A mesa-type bidirectional Shockley diode delimited on its two surfaces by a peripheral groove filled with a glassivation including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of the regions of the first conductivity type, at the interface between the substrate and the corresponding layer of the second conductivity type, each buried region being complementary in projection with the other; and a peripheral ring under the external periphery of each of the glassivations, of same doping profile as the buried regions. | 06-28-2012 |
20120161200 | DOUBLE-GROOVE BIDIRECTIONAL VERTICAL COMPONENT - A mesa-type bidirectional vertical power component, including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; first regions of the first conductivity type in each of the layers of the second conductivity type; and, at the periphery of each of its surfaces, two successive grooves, the internal groove crossing the layers of the second conductivity type, second doped regions of the first conductivity type being formed under the surface of the external grooves and having the same doping profile as the first regions. | 06-28-2012 |
20120267679 | STARTING STRUCTURE AND PROTECTION COMPONENT COMPRISING SUCH A STARTING STRUCTURE - A structure for starting a semiconductor component including a porous silicon layer in the upper surface of a semiconductor substrate. This porous silicon layer is contacted, on its upper surface side, by a metallization and, on its lower surface side, by a heavily-doped semiconductor region. | 10-25-2012 |
20130049065 | BI-DIRECTIONAL SWITCH WITH Q1 AND Q4 CONTROL - A vertical bidirectional switch of the type having its control referenced to the rear surface, including on its rear surface a first main electrode and on its front surface a second main electrode and a gate electrode, this switch being controllable by a positive voltage between its gate and its first electrode, wherein the gate electrode is arranged on the front surface of a via crossing the chip in which the switch is formed. | 02-28-2013 |
20130228822 | VERTICAL POWER COMPONENT - A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring. | 09-05-2013 |
20130320395 | HIGH-VOLTAGE VERTICAL POWER COMPONENT - A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer. | 12-05-2013 |
20140217462 | VERTICAL POWER COMPONENT - A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring. | 08-07-2014 |
20150084094 | SCR COMPONENT WITH TEMPERATURE-STABLE CHARACTERISTICS - An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The silicon region is interrupted in first areas where the material of the silicon layer comes into contact with the upper electrode, and is further interrupted in second areas filled with resistive porous silicon extending between the silicon layer and the main upper electrode. | 03-26-2015 |
20150108537 | HIGH-VOLTAGE VERTICAL POWER COMPONENT - A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. | 04-23-2015 |