Patent application number | Description | Published |
20150050503 | STORAGE STABLE RESIN FILMS AND FIBRE COMPOSITE COMPONENTS PRODUCED THEREFROM - The invention relates to a storage-stable resin film based on polyurethane systems having a very high characteristic number and fibre-composite components (composite components, moulded bodies) produced therefrom by compressing the resin film, in combination with fibre-reinforced materials such as woven fabrics and fleece, at high temperatures and under pressure, and to a method for the production thereof. | 02-19-2015 |
20150080530 | STORAGE-STABLE POLYURETHANE-PREPREGS AND FIBRE COMPOSITE COMPONENTS PRODUCED THEREFROM - The invention relates to storage-stable prepregs (preimpregnated fibers) based on low-viscosity polyurethane systems having a very high characteristic number and flat fibre composite components (moulded bodies; composite components) produced therefrom, which are obtained due to an impregnation method of fibre reinforced materials such as woven fabrics and fleece, and to a method for the production thereof. | 03-19-2015 |
20150218375 | FIBRE-REINFORCED COMPOSITE COMPONENTS AND PRODUCTION THEREOF - The invention relates to fibre-composite components, obtained for example by impregnating fibres with a reaction resin mixture of polyisocyanates, polyepoxides, polyols, latent catalysts and optionally additives. The invention also relates to a method for producing said components. | 08-06-2015 |
20150225566 | POLYURETHANE CASTING RESINS AND POTTING COMPOUNDS PRODUCED THEREFROM - The invention relates to polyurethane casting resins for producing polyurethane potting compounds, which can be obtained from a reaction mixture of polyisocyanates, polyepoxides, polyols, latent catalysts and optionally additives. The invention also relates to a method for producing said compounds. | 08-13-2015 |
Patent application number | Description | Published |
20120083121 | Fabrication of Replacement Metal Gate Devices - Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor. | 04-05-2012 |
20120083122 | Shallow Trench Isolation Chemical Mechanical Planarization - A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface. | 04-05-2012 |
20120083123 | Chemical Mechanical Planarization Processes For Fabrication of FINFET Devices - A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography. | 04-05-2012 |
20120083125 | Chemical Mechanical Planarization With Overburden Mask - Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer. | 04-05-2012 |