Patent application number | Description | Published |
20090014008 | Nasal Respiration Mask - According to the present invention, there is provided a nasal respiratory mask contacting with the face of a user for supplying respiratory positive-pressure gas to the nose of the user, comprising at least a part attached tightly to the face that is attached tightly to the face of the user; a frame-fitting part for fitting to a frame; and an elastic connecting part that connects elastically the part attached tightly to the face with the frame-fitting part, wherein a facial side of the elastic connecting part is kept apart from the frame-fitting part side thereof for a required distance even in the absence of applied respiratory positive pressure. | 01-15-2009 |
20090173343 | Nasal Respiratory Mask System and Connection/Disconnection Means Used Therein - The present invention relates to a nasal respiratory mask system comprising: a nasal mask that is tightly attached to the face of a user and serves as means for leading positive-pressure breathing gas to the nose of the user, a frame to keep the nasal mask at a predetermined position, and a headgear that is mounted on the head in order to attach the nasal mask tightly to the face; wherein, the headgear comprises, on the tip thereof, a headgear strap for adjusting the length of the headgear, the headgear strap comprises a headgear fastener that serves as means for connection/disconnection with the frame, the frame comprises a fastener catch that engages with the headgear fastener, and the fastener catch comprises an axisymmetric guide whose (rotation) axis is the insertion direction of the headgear fastener. The present invention provides a nasal respiratory mask system with which a headgear can be easily connected at the beginning of wearing, twisting of the headgear during wearing is prevented, and disassembly upon daily washing is easy. | 07-09-2009 |
20090250065 | HEADGEAR AND ITS MANUFACTURING METHOD - A headgear suitable for wearing a respiratory mask system wearing on the head of a user is provided, wherein it can be easily manufactured, the leakage of the positive pressure gas when pressurized is reduced, and a good wearing feel is achieved. The headgear is adapted to secure a respiratory mask, which contacts the face of the user to supply a positive pressure gas for respiration to the user, to the head of user. The headgear has a head mounted portion which is worn on the occipital of the user and a strap ( | 10-08-2009 |
20100012128 | RESPIRATORY MASK SYSTEM - A respiratory mask system is provided, in which while wearing a respiratory mask system, force generated by movement of a user's head and the like to induce laterally slipping a mask cushion may be reduced or absorbed. | 01-21-2010 |
20100043800 | Nasal respiratory mask system - A light weight nasal respiratory mask system securing airtightness of a mounting section between a nasal mask and a frame is provided. | 02-25-2010 |
Patent application number | Description | Published |
20110050304 | SEMICONDUCTOR APPARATUS - In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. | 03-03-2011 |
20110057819 | Semiconductor device having plural semiconductor chips laminated to each other - In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced. | 03-10-2011 |
20110093735 | Semiconductor memory device, method of adjusting the same and information processing system including the same - Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side. | 04-21-2011 |
20140056086 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF ADJUSTING THE SAME AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells. | 02-27-2014 |
20140132316 | SEMICONDUCTOR APPARATUS - In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes. | 05-15-2014 |
20140232438 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal. | 08-21-2014 |
20150116002 | SEMICONDUCTOR APPARATUS - A method for comparing phases between first and second clock signal includes the first clock signals to a first precharge circuit coupled between a first node and a first terminal to which a first voltage is applied. The first clock signal is supplied to a second precharge circuit coupled between a second node and the first terminal. The second clock signal is supplied to a first discharge circuit coupled between the first node and a second terminal to which a second voltage different from the first voltage is applied. The second clock signal is supplied to a second discharge circuit coupled between the second node and the second terminal. | 04-30-2015 |