Patent application number | Description | Published |
20100272827 | Method for transdermal iontophoretic delivery of chelated agents - Embodiments provide devices, systems and methods for the transdermal delivery of chelated compounds. One embodiment provides a method for the iontophoretic transdermal delivery of a chelated iron complex for the treatment of anemia. A first patch comprising an active electrode and a chelated iron complex is applied to the skin; a second patch containing an electrode is also applied. An electrical current is then delivered to the skin from the active electrode. The chelated complex is transported across the skin via electromotive force from the current, with the iron being substantially chromogenically unreactive with the skin during transport so that there is little or no tattooing of the skin due to the formation of insoluble oxidative products. The complex is then dissociated by phagocytosis or related process to release the iron where it may be bound by transferrin or ferritin and carried to other sites for storage or metabolic use. | 10-28-2010 |
20120177700 | Nanonized Iron Compositions and Methods of Use Thereof - Embodiments of the invention provide nanonized iron compositions for treatment of iron deficiency such as iron deficiency anemia. Many embodiments provide nanonized iron compositions which are sized to minimize adverse reaction such as immune response, adverse GI reaction and allergic reaction to iron compound included in the composition. The nanonized iron compositions can be used in a variety of drug delivery forms, including an oral dosage form, a transdermal patch, in an intravenous solution or in a dialysate for treatment of a patient with chronic kidney disease (CKD). Embodiments of the invention also provide methods of using the nanonized iron compositions for the treatment of iron deficiency in a patient in need thereof including patients with iron deficiency anemia and CKD. | 07-12-2012 |
20130325108 | BIODEGRADABLE MEDICAL IMPLANTS, POLYMER COMPOSITIONS AND METHODS OF USE - Embodiments of the invention provide compositions comprising bio degradable polymers, medical implants fabricated from these compositions and methods of using such implants. Many embodiments provide medical implants comprising a first polymer backbone having a first rate of biodegradation and a second polymer backbone having a second rate of biodegradation faster than the first rate. In some embodiments, the second backbone is configured to be replaced by a natural tissue layer. The first backbone provides a scaffold for the implant while the second backbone degrades. This scaffold can enhance mechanical properties of the implant including various aspects of mechanical strength such as tensile, bending, hoop and yield strength; and elasticity. The scaffold also serves to maintain a minimum level of structural support of the implant during the period of degradation of the second backbone or for the entire life of the implant so that the implant does not mechanically fail. | 12-05-2013 |
20150045721 | Method for Transdermal Iontophoretic Delivery of Chelated Agents - Embodiments provide devices, systems and methods for the transdermal delivery of chelated compounds. One embodiment provides a method for the iontophoretic transdermal delivery of a chelated iron complex for the treatment of anemia. A first patch comprising an active electrode and a chelated iron complex is applied to the skin; a second patch containing an electrode is also applied. An electrical current is then delivered to the skin from the active electrode. The chelated complex is transported across the skin via electromotive force from the current, with the iron being substantially chromogenically unreactive with the skin during transport so that there is little or no tattooing of the skin due to the formation of insoluble oxidative products. The complex is then dissociated by phagocytosis or related process to release the iron where it may be bound by transferrin or ferritin and carried to other sites for storage or metabolic use. | 02-12-2015 |
Patent application number | Description | Published |
20080212913 | HIGH SPEED SEMICONDUCTOR OPTICAL MODULATOR - The present invention provides an optical waveguide modulator. In one embodiment, the optical waveguide modulator includes a semiconductor planar optical waveguide core and doped semiconductor connecting paths located adjacent opposite sides of the core and capable of applying a voltage across the core. The optical waveguide core and connecting paths form a structure having back-to-back PN semiconductor junctions. In another embodiment, the optical waveguide modulator includes a semiconductor optical waveguide core including a ridge portion wherein the ridge portion has at least one PN semiconductor junction located therein. The optical waveguide modulator also includes one or more doped semiconductor connecting paths located laterally adjacent the ridge portion and capable of applying a voltage to the ridge portion. | 09-04-2008 |
20080279505 | OPTICAL COUPLING STRUCTURE - The present invention provides an apparatus and method for operation therefore. The apparatus, in one embodiment, includes an optical coupling structure disposed within a cladding region, wherein the optical coupling structure includes a first guiding portion and a second guiding portion. In this embodiment the first guiding portion has a first end proximate a core of a planar waveguide, and a second end proximate the second guiding portion and having a first thickness. Moreover, in this embodiment the second guiding portion has a first end proximate the first guiding portion and a second end, the second end of the second guiding portion having a second thickness less than the first thickness. | 11-13-2008 |
20090003770 | VERTICAL OPTICAL COUPLING STRUCTURE - The present disclosure provides an apparatus, method of manufacturing an apparatus, and method for operation of the same. The apparatus, in one embodiment, includes an optical coupling structure disposed within a cladding region, wherein the optical coupling structure includes a first guiding portion and a second guiding portion. In this embodiment, the first guiding portion is located on a first plane and tapers from a first greater width to a first lesser width in a first direction. The second guiding portion, in turn, is located on a second different plane and tapers from a second greater width to a second lesser width in a second opposite direction. | 01-01-2009 |
20090161113 | INTEGRATED OPTOELECTRONIC SYSTEM FOR AUTOMATIC CALIBRATION OF AN OPTICAL DEVICE - An apparatus and method for automated calibration of an optical device are disclosed. The apparatus is an integrated optoelectronic system that includes input and output optical waveguides, a tunable optical device, an optical source, an optical detector, and an electronic controller formed on a single substrate. The tunable optical device has one or more tuning elements for varying one or more characteristics of the device. The optical source is coupled to the input waveguide for providing a calibration signal to the device. The optical detector is coupled to the output optical waveguide for measuring an intensity of the optical signal output by the device in response to receiving the calibration signal. The electronic controller is configured to perform a calibration of the device by varying a parameter of each tuning element and to receive intensity measurements of the optical signal output by the device as a function of the varied parameter. | 06-25-2009 |
20090214223 | CMOS-COMPATIBLE TUNABLE MICROWAVE PHOTONIC BAND-STOP FILTER - According to one embodiment, a microwave photonic band-stop (MPBS) filter uses an electrical input signal to drive an optical Mach-Zehnder modulator. A modulated optical carrier produced by the modulator is applied to an optical filter having at least two tunable spectral attenuation bands that are located substantially symmetrically on either side of the carrier frequency. The resulting filtered optical signal is applied to an optical-to-electrical (O/E) converter to produce an electrical output signal. | 08-27-2009 |
Patent application number | Description | Published |
20080266263 | Human-To-Mobile Interfaces - A method of character recognition for a personal computing device comprising a user interface capable of receiving inputs that are to be recognised through data input means which are receptive to keyed, tapped or a stylus input, said device being adapted to facilitate a reduction in the number of physical keying actions, tapping actions or gestures required to create a data string to less than the number of characters within said data string: storing a set of data strings each with a priority indicator associated therewith, wherein the indicator is a measure of a plurality of derivatives associated with the data string; recognising an event; looking up the most likely subsequent data string to follow the event from the set of data strings based on one or more of the plurality of derivatives; ordering the data strings for display based on the priority indicator of that data string; if the required subsequent data string is included in the list selecting the required subsequent data string; if the required subsequent data string is not included in the list entering a event and repeating steps b to e; updating the priority indicator of the selected data string; updating the set of data strings based on the updated priority indicator. | 10-30-2008 |
20090055732 | Human-to-mobile interfaces - A method of for a mobile telephone data input apparatus comprising a plurality of data input keys having multi-character indicia, said method adapted to facilitate a reduction in the number of user interactions required to create a given data string to less than the number of characters within said data string, the method comprising the following steps: storing a set of data strings each with a priority indicator associated therewith, wherein the indicator is a measure of a plurality of derivatives associated with the data string; recognising an event; looking up the most likely subsequent data string to follow the event from the set of data strings based on one or more of the plurality of derivatives; ordering the data strings for display based on the priority indicator of that data string; if the required subsequent data string is included in the list selecting the required subsequent data string; if the required subsequent data string is not included in the list entering a event and repeating steps b to e; updating the priority indicator of the selected data string; updating the set of data strings based on the updated priority indicator. | 02-26-2009 |
20150095127 | INTERCONNECTING ENHANCED AND DIVERSIFIED COMMUNICATIONS WITH COMMERCIAL APPLICATIONS - A system for interconnecting enhanced and diversified communications with commercial applications using efficient and user-friendly features and methods by which users can create, share, and proliferate symbols, use translations, message contractions, message expansions, hidden messages, scrolling or bill-boarding messages, timed messages, Morse messages, and inter-language translations, all using various forms of formatting and presentation configurations. Such system and communications are used and made amongst various social groupings, providing benefits and incentives for usage of the system, and personalized consumer insight that links to commercial applications | 04-02-2015 |
20150242873 | INTERCONNECTING ENHANCED AND DIVERSIFIED COMMUNICATIONS WITH COMMERCIAL APPLICATIONS - A system for interconnecting enhanced and diversified communications with commercial applications using efficient and user-friendly features and methods by which users can create, share, and proliferate symbols, use translations, message contractions, message expansions, hidden messages, scrolling or bill-boarding messages, timed messages, Morse messages, and inter-language translations, all using various forms of formatting and presentation configurations. Such system and communications are used and made amongst various social groupings, providing benefits and incentives for usage of the system, and personalized consumer insight that links to commercial applications | 08-27-2015 |
Patent application number | Description | Published |
20110153942 | REDUCING IMPLEMENTATION COSTS OF COMMUNICATING CACHE INVALIDATION INFORMATION IN A MULTICORE PROCESSOR - A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In response to invalidating a given lower-level cache line, the lower-level cache may be configured to convey a sequence including several invalidation packets to the processor cores via an interface, where each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and where the interface is narrower than an interface capable of concurrently conveying all invalidation information corresponding to the given lower-level cache line. Each invalidation packet may include invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores. | 06-23-2011 |
20110185125 | RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR - A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently. | 07-28-2011 |
20120239883 | RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR - A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure. | 09-20-2012 |
20120331265 | Apparatus and Method for Accelerated Hardware Page Table Walk - A method of walking page tables includes comparing a virtual address to a plurality of virtual address bit segments to identify a match. Each virtual address bit segment is associated with a page table level that has a page table base address. A designated page table base address is received in response to the match. The page table walk starts at the designated page table, thereby skipping over earlier page tables. | 12-27-2012 |
20130132702 | Processor with Kernel Mode Access to User Space Virtual Addresses - A computer includes a memory and a processor connected to the memory. The processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes to allow kernel mode access to user space virtual addresses for enhanced kernel mode memory capacity. | 05-23-2013 |
20130263124 | Apparatus and Method for Guest and Root Register Sharing in a Virtual Machine - A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources. | 10-03-2013 |
20140068138 | Embedded Processor with Virtualized Security Controls Using Guest Identifications, a Common Kernel Address Space and Operational Permissions - A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection. | 03-06-2014 |
20140250289 | Branch Target Buffer With Efficient Return Prediction Capability - Improved branch target buffers (BTBs) and methods of processing data in a microprocessor with a pipeline are provided. According to various embodiments, a BTB is provided that includes a non-return buffer, a return buffer, and a multiplexer. The non-return buffer is designed to store a multiple of non-return entries. Each non-return entry corresponds to a non-return type instruction. The return buffer is designed to store a plurality of return entries that each correspond to a return type instruction. Additionally, the return buffer may generate a control signal. The multiplexer also generates a control signal and outputs either data from the non-return buffer or data from a return prediction stack (RPS). Whether the multiplexer returns data from the non-return buffer or the RPS depends on the control signal. | 09-04-2014 |