Patent application number | Description | Published |
20080197400 | Transistor constructions and processing methods - A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening. | 08-21-2008 |
20080225589 | Memory page boosting method, device and system - A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells. | 09-18-2008 |
20080253187 | MULTIPLE SELECT GATE ARCHITECTURE - Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing multiple series-coupled select gates, each gate can be made using smaller features sizes while achieving the same level of protection against GIDL and other forms of current leakage. By reducing the feature size of the select gates, the footprint of the strings of memory cells can be reduced, thereby facilitating smaller memory device sizing. Further reductions in device sizing may be achieved utilizing a staggered self-aligned bit line contact configuration. | 10-16-2008 |
20080253188 | PROGRAMMING METHOD TO REDUCE GATE COUPLING INTERFERENCE FOR NON-VOLATILE MEMORY - A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory cells, so that the coupling effect results in the desired target threshold voltages for the cells. In one embodiment of the present invention, memory cell coupling is compensated for by adjusting programming level of one or more memory cells of a first page a memory array to a higher or lower threshold verify target voltage given the data/programming level to be written to directly adjacent memory cells of a second page, so that coupling between the directly adjacent memory cells of the first and second pages brings the memory cells of first page to their final target programming level. | 10-16-2008 |
20080266971 | PROGRAMMING A FLASH MEMORY DEVICE - An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the program/verify operation. The second verify read operation uses a verify voltage that is substantially close to the maximum verify voltage used during the program/verify step. | 10-30-2008 |
20080266972 | PROGRAMMING A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial programming pulse, a verify operation determines if the cell has been programmed. If the cell is still erased, the initial programming voltage is increased by the step voltage. The step voltage for the lowest word line near the source line is lower than the step voltage for the word line closest to the drain line. | 10-30-2008 |
20080273389 | Flash memory cells, NAND cell units, methods of forming NAND cell units, and methods of programming NAND cell unit strings - Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate types, and capacitively coupled with control gates of the first gate types. The second gate types may be multilevel cell (MLC) devices, and pass voltage applied to the control gates of the first gate types may be utilized to reduce programming voltages utilized to reach memory states of the MLC devices. Some embodiments include NAND cell units, and some embodiments include methods of forming NAND cell units. Also, some embodiments include methods of programming NAND cell unit string gates in which programming voltage applied to a first string gate is held below a threshold, and pass voltage applied to an adjacent string gate is increased and utilized to program the first string gate. | 11-06-2008 |
20080291730 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial V | 11-27-2008 |
20080304322 | NAND FLASH MEMORY CELL PROGRAMMING - A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block. Methods for pre-charging word lines in unselected array blocks are described. | 12-11-2008 |
20090011560 | MULTIPLE SELECT GATE ARCHITECTURE WITH SELECT GATES OF DIFFERENT LENGTHS - The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled in series with the first select gate. A length of the second select gate is greater than a length of the first select gate. | 01-08-2009 |
20090034337 | METHOD, APPARATUS, AND SYSTEM FOR IMPROVED READ OPERATION IN MEMORY - Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent a target cell, and reading the target cell of the memory array using a wordline voltage value based on the threshold voltage value of the adjacent cell. Additional apparatus, systems, and methods are disclosed. | 02-05-2009 |
20090045449 | FINNED MEMORY CELLS - For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching. | 02-19-2009 |
20090046507 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage. | 02-19-2009 |
20090068812 | Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 03-12-2009 |
20090109756 | MEMORY DEVICE WITH VARIABLE TRIM SETTING - A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated subset. Circuitry is operable to program at least a portion of a selected subset using the associated trim parameter. A method for operating a memory device includes storing at least one trim parameter for each of a plurality of subsets of a memory array in the memory device within each of the subsets. At least a portion of a selected subset is programmed based on the at least one trim parameter associated with the selected subset. | 04-30-2009 |
20090122607 | ERASE OPERATION IN A FLASH DRIVE MEMORY - A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verified. Adjacent cells are programmed and verified. The parasitic capacitance between the target cells and the adjacent cells causes the threshold voltage of the target cell to increase to a new threshold voltage with the programming of the adjacent cells. A difference between the new threshold voltage and the first threshold voltage is determined. If the difference is greater than or equal to a predetermined threshold, the target cell is soft programmed until the difference is less than the predetermined threshold. | 05-14-2009 |
20090196106 | MEM SUSPENDED GATE NON-VOLATILE MEMORY - A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention. | 08-06-2009 |
20090273019 | MEMORY DEVICE TRANSISTORS - Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric provided for the floating gate transistors. | 11-05-2009 |
20090273979 | PROGRAMMING METHOD TO REDUCE WORD LINE TO WORD LINE BREAKDOWN FOR NAND FLASH - A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order to reduce voltage differences between the word lines of the memory cell string or array during a programming cycle. This allows the word line to word line voltage differential to be reduced and thus decreases the likelihood of breakdown or punch through of the insulator materials placed between the adjacent word lines. | 11-05-2009 |
20090316486 | PROGRAM AND READ TRIM SETTING - A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability. | 12-24-2009 |
20100008154 | INTERCONNECTING BIT LINES IN MEMORY DEVICES FOR MULTIPLEXING - An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs. | 01-14-2010 |
20100039862 | READ OPERATION FOR NAND MEMORY - Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to a source line selectively coupled to a bit line through a string of series-coupled non-volatile memory cells containing a memory cell targeted for reading, and where a second, different, potential is supplied to other source lines selectively coupled to the bit line through other strings of series-coupled non-volatile memory cells not containing the target memory cell. Supplying a different potential to the other source lines facilitates mitigation of current leakage between the other source lines and the bit line while sensing a data value of the target memory cell. | 02-18-2010 |
20100046305 | ERASE OPERATION IN A FLASH DRIVE MEMORY - A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verified. Adjacent cells are programmed and verified. The parasitic capacitance between the target cells and the adjacent cells causes the threshold voltage of the target cell to increase to a new threshold voltage with the programming of the adjacent cells. A difference between the new threshold voltage and the first threshold voltage is determined. If the difference is greater than or equal to a predetermined threshold, the target cell is soft programmed until the difference is less than the predetermined threshold. | 02-25-2010 |
20100074021 | NAND FLASH MEMORY PROGRAMMING - A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages. | 03-25-2010 |
20100091544 | COUPLINGS WITHIN MEMORY DEVICES - A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed. | 04-15-2010 |
20100142268 | PROGRAMMING METHOD TO REDUCE GATE COUPLING INTERFERENCE FOR NON-VOLATILE MEMORY - A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory cells, so that the coupling effect results in the desired target threshold voltages for the cells. In one embodiment of the present invention, memory cell coupling is compensated for by adjusting programming level of one or more memory cells of a first page a memory array to a higher or lower threshold verify target voltage given the data/programming level to be written to directly adjacent memory cells of a second page, so that coupling between the directly adjacent memory cells of the first and second pages brings the memory cells of first page to their final target programming level. | 06-10-2010 |
20100142285 | REDUCING READ FAILURE IN A MEMORY DEVICE - Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines. | 06-10-2010 |
20100202210 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial V | 08-12-2010 |
20100232222 | MEMORY PAGE BOOSTING METHOD, DEVICE AND SYSTEM - A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells. | 09-16-2010 |
20100291766 | Transistor Constructions and Processing Methods - A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening. | 11-18-2010 |
20100320523 | FINNED MEMORY CELLS - For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching. | 12-23-2010 |
20110013463 | Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 01-20-2011 |
20110096597 | PROGRAMMING A FLASH MEMORY DEVICE - An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the program/verify operation. The second verify read operation uses a verify voltage that is substantially close to the maximum verify voltage used during the program/verify step. | 04-28-2011 |
20110149658 | METHOD, APPARATUS, AND SYSTEM FOR IMPROVED READ OPERATION IN MEMORY - Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent a target cell, and reading the target cell of the memory array using a wordline voltage value based on the threshold voltage value of the adjacent cell. Additional apparatus, systems, and methods are described. | 06-23-2011 |
20110222352 | METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE TO REDUCE FLOATING-GATE-TO-FLOATING-GATE COUPLING EFFECT - A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The method: programs the lower page of predetermined memory cells with first predetermined data and the upper page with second predetermined data. One of the lower page or the upper page of the predetermined memory cells is reprogrammed with the first or second predetermined data, respectively. | 09-15-2011 |
20110230033 | FABRICATION OF FINNED MEMORY ARRAYS - Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper surface of the fins. A first dielectric layer is formed overlying the isotropically etched fins. A first conductive layer is formed overlying the first dielectric layer. A second dielectric layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the second dielectric layer. | 09-22-2011 |
20110233686 | INTERCONNECTING BIT LINES IN MEMORY DEVICES FOR MULTIPLEXING - An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs. | 09-29-2011 |
20110242897 | PROGRAM AND READ TRIM SETTING - A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability. | 10-06-2011 |
20110260236 | Transistor Constructions and Processing Methods - A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening. | 10-27-2011 |
20110266610 | MEMORY DEVICES HAVING REDUCED INTERFERENCE BETWEEN FLOATING GATES AND METHODS OF FABRICATING SUCH DEVICES - A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array. | 11-03-2011 |
20110298035 | MEMORY DEVICE TRANSISTORS - Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric provided for the floating gate transistors. | 12-08-2011 |
20120113722 | Selecting programming voltages in response to at least a data latch in communication with a sense amplifier - Memory devices and methods of programming memory cells including selecting a voltage to apply to a control gate of the memory cell during programming of a data value of a sense amplifier to the memory cell in response to at least a data value contained in a data latch that is in communication with the sense amplifier. | 05-10-2012 |
20120132979 | Memory Devices And Methods Of Forming Memory Devices - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 05-31-2012 |
20120176838 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage. | 07-12-2012 |
20120258574 | COUPLINGS WITHIN MEMORY DEVICES - A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed. | 10-11-2012 |
20120275227 | PHOTOSENSITIVE COMPOSITION AND COMPOUND FOR USE IN THE PHOTOSENESITIVE COMPOSITION - A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages. | 11-01-2012 |
20130009233 | Transistor Constructions and Processing Methods - A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening. | 01-10-2013 |
20130193505 | Memory Devices and Methods of Forming Memory Devices - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 08-01-2013 |
20130237031 | MEMORY DEVICES HAVING REDUCED INTERFERENCE BETWEEN FLOATING GATES AND METHODS OF FABRICATING SUCH DEVICES - A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array. | 09-12-2013 |
20140035021 | Memory Devices Comprising Word Line Structures, At Least One Select Gate Structure, and a Plurality Of Doped Regions - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 02-06-2014 |
20140254265 | Flash Memory Cells, NAND Cell Units, Methods of Forming NAND Cell Units, and Methods of Programming NAND Cell Unit Strings - Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate types, and capacitively coupled with control gates of the first gate types. The second gate types may be multilevel cell (MLC) devices, and pass voltage applied to the control gates of the first gate types may be utilized to reduce programming voltages utilized to reach memory states of the MLC devices. Some embodiments include NAND cell units, and some embodiments include methods of forming NAND cell units. Also, some embodiments include methods of programming NAND cell unit string gates in which programming voltage applied to a first string gate is held below a threshold, and pass voltage applied to an adjacent string gate is increased and utilized to program the first string gate. | 09-11-2014 |