Patent application number | Description | Published |
20090009926 | Capacitor Structure - One or more embodiments relate to a capacitor structure comprising a first and second capacitor electrode. The first electrode may include a conductive strip having at least one wider portion and at least one narrower portion. The second electrode may include a conductive strip having at least one wider portion and at least one narrower portion. | 01-08-2009 |
20090014832 | Semiconductor Device with Reduced Capacitance Tolerance Value - A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations. | 01-15-2009 |
20090141424 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via. | 06-04-2009 |
20090230507 | MIM Capacitors in Semiconductor Components - Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance. | 09-17-2009 |
20090239375 | Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 09-24-2009 |
20100072572 | SEMICONDUCTOR DEVICE - One or more embodiments relate to a semiconductor device, comprising: a inductor coil including a winding; and a capacitor arrangement including at least one capacitor, the capacitor arrangement electrically coupled to the inductor coil, the footprint of the capacitor arrangement at least partially overlapping the footprint of the inductor coil. | 03-25-2010 |
20100295154 | Capacitor Structure - One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates. | 11-25-2010 |
20110086487 | Semiconductor Device with Reduced Capacitance Tolerance Value - A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations. | 04-14-2011 |
20120025382 | Devices Formed With Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 02-02-2012 |
20120091560 | MIM Capacitors in Semiconductor Components - Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance. | 04-19-2012 |
20120256274 | Schottky Diodes Having Metal Gate Electrodes And Methods of Formation Thereof - In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region. | 10-11-2012 |
20120267762 | Capacitor Structure - One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates. | 10-25-2012 |
20130240884 | DETECTION OF ENVIRONMENTAL CONDITIONS IN A SEMICONDUCTOR CHIP - A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip. | 09-19-2013 |
20130307091 | Schottky Diodes Having Metal Gate Electrodes and Methods of Formation Thereof - In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region. | 11-21-2013 |
20150084196 | Devices Formed With Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 03-26-2015 |