Patent application number | Description | Published |
20080204123 | SEMICONDUCTOR DEVICE - A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage, a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage, an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage, and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a conductive state brought by a gate substantially connected to the ground voltage to maintain the low voltage to be substantially at the ground voltage until a possibility that the low voltage rises higher than the ground voltage is eliminated. | 08-28-2008 |
20090009446 | Driver circuit, electro-optical device, and electronic instrument - A driver circuit for driving source lines of an electro-optical device includes first and second source short-circuit circuits that respectively short-circuit first and second source lines and a source short-circuit node, a source charge storage short-circuit circuit that short-circuits a source charge storage node connected with one end of a source capacitor and the source short-circuit node, a voltage setting circuit that supplies a given voltage to the source charge storage node, and a node short-circuit circuit that short-circuits a common electrode voltage output node and the source short-circuit node, a voltage output to a common electrode of the electro-optical device provided opposite to a pixel electrode through an electro-optical element being applied to the common electrode voltage output node. | 01-08-2009 |
20090096491 | DRIVER CIRCUIT, DATA DRIVER, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC INSTRUMENT - A driver circuit includes a first capacitor provided between a first node and a reference node, a second capacitor provided between a second node and the reference node, a first switch element provided between the first node and an input node, a second switch element provided between the first node and an analog reference power supply, a third switch element provided between the second node and an output node, a fourth switch element provided between the second node and the analog reference power supply, and a fifth switch element provided between the output node and the reference node. A first capacitor area and a second capacitor area are disposed along a first direction. The first switch element and the second switch element are disposed in a third direction with respect to the first capacitor area and the second capacitor area. The third switch element and the fourth switch element are disposed in the first direction with respect to the first capacitor area and the second capacitor area. A reference node line is provided in a second direction with respect to the first switch element, the second switch element, the third switch element, and the fourth switch element. | 04-16-2009 |
20090096817 | D/A CONVERSION CIRCUIT, DATA DRIVER, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC INSTRUMENT - A D/A conversion circuit includes a first D/A converter and a second D/A converter that respectively output a first voltage and a second voltage. An ith two-input selector among a plurality of input selectors of the first D/A converter selects a (4i+1)th input voltage or a (4i+3)th input voltage based on input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage. An ith three-input selector among a plurality of three-input selectors of the second D/A converter selects a 4ith input voltage, a (4i+2)th input voltage, or a (4i+4)th input voltage based on the input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage. | 04-16-2009 |
20090096818 | DATA DRIVER, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC INSTRUMENT - A data driver includes a D/A conversion circuit, a switch circuit, and a data line driver circuit. The switch circuit includes a first switch element provided between a first voltage output node of the D/A conversion circuit and a first input node of a grayscale generation amplifier, a second switch element that is provided between a second voltage output node of the D/A conversion circuit and the first input node and is exclusively turned ON/OFF with respect to the first switch element, a third switch element provided between the first voltage output node and a second input node, and a fourth switch element that is provided between the second voltage output node and the second input node and is exclusively turned ON/OFF with respect to the third switch element. | 04-16-2009 |
20090160849 | INTEGRATED CIRCUIT DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT - An integrated circuit device includes first to Nth data driver blocks that are disposed along a first direction. Each of the first to Nth data driver blocks includes first to Mth sub-driver blocks. Each of the sub-driver blocks includes a D/A conversion circuit that receives image data and D/A-converts the image data, and first to Lth data line driver circuits that are disposed along the first direction in a second direction with respect to the D/A conversion circuit and share the D/A conversion circuit. | 06-25-2009 |
20090160881 | INTEGRATED CIRCUIT DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT - An integrated circuit device includes first to Nth memory blocks that are disposed along a first direction, and first to Nth data driver blocks that are disposed along the first direction in a second direction with respect to the first to Nth memory blocks. A Jth memory block among the first to Nth memory blocks dot-sequentially reads subpixel image data and outputs the subpixel image data to a corresponding Jth data driver block among the first to Nth data driver blocks, the subpixel image data being image data corresponding to at least one subpixel. The Jth data driver block receives the subpixel image data from the Jth memory block, and outputs a data signal corresponding to the subpixel image data. | 06-25-2009 |
20090160882 | INTEGRATED CIRCUIT DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT - An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks. An analog reference power supply line is provided in an area of the data driver along the first direction, | 06-25-2009 |
20090212820 | DECODER CIRCUIT, DECODING METHOD, OUTPUT CIRCUIT, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT - A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion. | 08-27-2009 |