Luo, Hsinchu
Boren Luo, Hsinchu TW
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20110230998 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
20110231804 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
Chih-Wei Luo, Hsinchu TW
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20130299466 | Method for Forming Superior Local Conductivity in Self-Organized Nanodots of Transparent Conductive Film by Femtosecond Laser - A simple method is developed in the present invention for fabricating periodic ripple microstructures on the surface of an ITO film by using single-beam femtosecond laser pulses. The periodic ripple microstructures composed of self-organized nanodots can be directly fabricated through the irradiation of the femtosecond laser, without scanning. The ripple spacing of ˜800 nm, ˜400 nm and ˜200 nm observed in the periodic ripple microstructures can be attributed to the interference between the incident light and the scattering light of the femtosecond laser from the surface of the ITO film. In the present invention, the self-organized dots are formed by the constructive interference formed in the surface of the ITO film, where includes higher energy to break the In—O and Sn—O bonds and then form the In—In bonds. Therefore, the dots have higher surface current greater than other disconstructive regions of the ITO film. | 11-14-2013 |
Chiou-Mei Luo, Hsinchu TW
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20150357290 | LAMINAR STRUCTURE OF SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - A laminar structure of semiconductors comprises a substrate, an epitaxial layer, a protective layer, a first layer and a second layer. The epitaxial layer is arranged above the substrate and the protective layer is arranged below the substrate. Thermal expansion coefficients of the epitaxial layer and the protective layer are simultaneously greater than or less than that of the substrate. The first layer is arranged between the substrate and the protective layer; and the second layer is arranged between the substrate and the epitaxial layer, wherein the band gap of the first layer and the second layer are both greater than 3 eV. By a protective layer arranged below the substrate, stress generated between the substrate and the epitaxial layer can be reduced to prevent occurrence of bending or crack. Therefore, yield can be promoted and costs can be reduced. A manufacturing method thereof is also herein provided. | 12-10-2015 |
Guang-Li Luo, Hsinchu TW
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20090221144 | Manufacturing method for nano scale Ge metal structure - Manufacturing methods for nano scale Ge include: Form dielectric layer on the substrate surface, then etch the dielectric layer to form openings of three different dimensions, then use chemical vapor deposition process to deposit Ge metal layer to cover the substrate, dielectric layer and the openings; then on the opening of three different dimensions, nano-dot, nano-disk and nano-ring are formed. | 09-03-2009 |
20140131768 | BRIDGE STRUCTURE - A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block. | 05-15-2014 |
20140374834 | GERMANIUM STRUCTURE, GERMANIUM FIN FIELD EFFECT TRANSISTOR STRUCTURE AND GERMANIUM COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR STRUCTURE - A germanium (Ge) structure includes a substrate, a Ge layer and at least a Ge spatial structure. The Ge layer is formed on the substrate, and a surface of the Ge layer is a Ge {110} lattice plane. The Ge spatial structure is formed in the Ge layer and includes a top surface and a sidewall surface, wherein the top surface is a Ge {110} lattice plane and the sidewall surface is perpendicular to the top surface. An axis is formed at a junction of the sidewall surface and the top surface, and an extensive direction of the axis is parallel to a Ge [112] lattice vector on the surface of the Ge layer, therefore the sidewall surface is a Ge {111} lattice plane. Because Ge {111} surface channels have very high electron mobility, this Ge spatial structure may be applied for fabricating high-performance Ge semiconductor devices. | 12-25-2014 |
Huan Chin Luo, Hsinchu TW
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20110149533 | INTEGRATED CIRCUIT FILM FOR SMART CARD - An integrated circuit (IC) film for a smart card is provided. The IC film includes a flexible printed circuit (FPC) board, first electrical contacts, second electrical contacts, and an IC chip. The first electrical contacts are disposed on a first side of the FPC board, and the second electrical contacts are disposed on a second side of the FPC board. The IC chip is disposed on the FPC board and bonded to the leads of the FPC board to thereby form electrical connection. The total thickness of the FPC board and the chip is not larger than 0.5 mm. | 06-23-2011 |
Ruei-Liang Luo, Hsinchu TW
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20090294684 | ULTRAVIOLET INTENSITY DETECTING METHOD, FABRICATING DISPLAY APPARATUS METHOD AND DISPLAY APPARATUS USING THE SAME - A display apparatus is provided. The display apparatus is used for detecting an ultraviolet (UV) intensity. The display apparatus includes a lower-substrate, an upper-substrate and a processing unit. The lower-substrate includes a first, a second and a third photo sensors for detecting an intensity of the light in a first, a second and a third bands and converting the intensity of the light in the first, the second and the third bands into a first, a second and a third currents respectively, wherein the ranges of the second and the third bands are comprised within the range of the first band. The upper-substrate is disposed opposite to the lower-substrate. The processing unit is coupled to the first, the second and the third photo sensors, for receiving and processing the first, the second and the third currents so as to obtain the UV intensity. | 12-03-2009 |
Shing-Ann Luo, Hsinchu TW
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20090008703 | NON-VOLATILE MEMORY CELL AND FABRICATING METHOD THEREOF - A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer. | 01-08-2009 |
20090033915 | APC SYSTEM AND MULTIVARIATE MONITORING METHOD FOR PLASMA PROCESS MACHINE - An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system. | 02-05-2009 |
20090299668 | APC SYSTEM AND MULTIVARIATE MONITORING METHOD FOR PLASMA PROCESS MACHINE - An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system. | 12-03-2009 |
20100041245 | HDP-CVD PROCESS, FILLING-IN PROCESS UTILIZING HDP-CVD, AND HDP-CVD SYSTEM - An HDP-CVD process is described, including a deposition step conducted in an HDP-CVD chamber and a pre-heating step that is performed outside of the HDP-CVD chamber before the deposition step and pre-heats a wafer to a temperature higher than room temperature and required in the HDP-CVD process deposition step. | 02-18-2010 |
20100252878 | NON-VOLATILE MEMORY CELL - A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer. | 10-07-2010 |
20120000423 | HDP-CVD SYSTEM - An HDP-CVD system is described, including an HDP-CVD chamber for depositing a material on a wafer, and a pre-heating chamber disposed outside of the HDP-CVD chamber to pre-heat the wafer, before the wafer is loaded in the HDP-CVD chamber, to a temperature higher than room temperature and required in the deposition step to be conducted in the HDP-CVD chamber. The pre-heating chamber is equipped with a heating lamp for the pre-heating. The wafer has been formed with a trench before being pre-heated. | 01-05-2012 |
Tian-Shuan Luo, Hsinchu TW
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20100176434 | DATA STORAGE STRUCTURE, MEMORY DEVICE AND PROCESS FOR FABRICATING MEMORY DEVICE - A memory device is described, including a substrate, data storage structures over the substrate, control gates over the data storage structures, and a dielectric layer between the data storage structures and the control gates, wherein each data storage structure includes a lower part and an upper part narrower than the lower part. A process for fabricating the memory device is also described, wherein formation of the data storage structures includes recessing portions of a data storage layer to form respective upper parts of the data storage structures and then dividing the recessed portions of the data storage layer to form respective lower parts of the data storage structures. | 07-15-2010 |
Tseng Chin Luo, Hsinchu TW
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20120074981 | METHOD AND APPARATUS FOR DEVICE PARAMETER MEASUREMENT - A method of measuring a parameter of a device in a circuit includes providing a device under test (DUT). The DUT includes a metal oxide semiconductor (MOS) transistor having a gate, a source, and a drain coupled to a first voltage supply node. The method further includes coupling a constant current source to the source of the transistor, coupling an operational amplifier to the transistor, and measuring a parameter of the transistor. | 03-29-2012 |
Tzuo-Liang Luo, Hsinchu TW
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20090139964 | WIRE-RECEIVING MECHANISM - A wire-receiving mechanism for holding electrical wire used to cut or burn through a metal work piece in wire electrical discharge machines (WEDMs) is disclosed. A passive wheel and an active wheel are disposed side by side with one another in a case body, the active wheel being capable of causing the passive wheel to rotate, wherein one side of the passive wheel has a driving unit defined thereon. The driving unit is disposed to penetrate through one side of the case body, and includes a driving member disposed to one side of the case body, an action member connected to the driving member and a sliding member connected to the action member for pushing the passive wheel, wherein a pretension spring is disposed at one side of the sliding member for controlling the gap between the passive wheel and the active wheel such that the processing wires can be stably held and conveyed. | 06-04-2009 |
20100103764 | WORKING TROUGH AND METHOD FOR MAINTAINING UNIFORM TEMPERATURE OF WORKING FLUID - The invention provides a working trough and a method for maintaining a uniform temperature of a working fluid. The working trough is applied to an electrical discharge machine that performs wire cutting using the working fluid. The method for maintaining a uniform temperature of the working fluid is applied to the working trough and characterized by forming opening structures in a receiving slot of the working trough such that a spiral swirl having a predetermined height is allowed to be formed in the working fluid, thereby maintaining a uniform temperature of the working fluid in the receiving slot when a wire cutting process is performed in the working fluid by the electrical discharge machine. The disturbance of the spiral swirl also facilitates the discharge of scraps. The present invention further has an advantage of low cost. | 04-29-2010 |
Xiaodong Luo, Hsinchu TW
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20150077598 | IMAGE SENSOR AND COMPENSATION METHOD THEREOF - An image sensor is provided. The image sensor includes a pixel array, an analog-to-digital converter, and a processor. The analog-to-digital converter converts a black level reference signal and a pix signal from the pixel array into a first digital signal and a second digital signal, respectively. The processor obtains a black level reference value according to the first digital signal, and obtains a compensation coefficient according to the black level reference value, a maximum digital level of the analog-to-digital converter and a full signal range value. The processor obtains pix data according to the compensation coefficient, the black level reference value and the second digital signal. | 03-19-2015 |
20150077604 | Image Sensor and Adjustment Method Thereof - An image sensor is provided. The image sensor includes a pixel array, a sense amplifier, an analog-to-digital converter, a processor and a voltage generator. The sense amplifier obtains a first signal according to a pixel signal from the pixel array and a reference voltage, wherein the reference voltage has a first voltage level. The analog-to-digital converter converts the first signal into a first digital signal. The processor provides a feedback signal according to the first digital signal. The voltage generator adjusts the reference voltage to a second voltage level corresponding to the feedback signal. The sense amplifier removes a direct current (DC) bias voltage from the pixel signal according to the reference signal having the second voltage level. | 03-19-2015 |
Yuan-Syun Luo, Hsinchu TW
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20110029992 | Casing assembling structure of optical disc drive - A casing assembling structure of an optical disc drive is provided to comprise a bottom cover; a top cover combined with the bottom cover to form a space, wherein the top cover has a first side wall and a fixing portion, which is extended from the first side wall and is positioned under the bottom cover; and a first screw screwed on the fixing portion, wherein the top cover, the first side wall and the fixing portion are formed as a integral. | 02-03-2011 |
20130185741 | SLIM-TYPE OPTICAL DISC DRIVE - A slim-type optical disc drive includes a casing and a tray. A first circuit board is disposed within the casing. A second circuit board is disposed on the tray. A spring switch is disposed on the second circuit board. A first end of the spring switch is fixed on the second circuit board. A resistor is connected between the first end of the spring switch and a first power source. A second end of the spring switch is extended outside the second circuit board. In a tray-out status, the second end of the spring switch is not contacted with any object, so that a first status signal is generated. In a tray-in status, the second end of the spring switch is contacted with a conducting zone of a second power source, so that a second status signal is generated. | 07-18-2013 |