Patent application number | Description | Published |
20080284491 | Integrated Circuit, Electronic Device and Integrated Circuit Control Method - An integrated circuit ( | 11-20-2008 |
20080309541 | Flash Analog-to-Digital Converter - A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals. | 12-18-2008 |
20090013116 | DATA COMMUNICATION METHOD, DATA TRANSMISSION AND RECEPTION DEVICE AND SYSTEM | 01-08-2009 |
20110051542 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ACCESSING THE MEMORY CIRCUITS - A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. A sense amplifier is coupled with the bit line. The sense amplifier is capable of precharging the bit line to a first voltage that is substantially equal to and higher than a threshold voltage (V | 03-03-2011 |
20110069570 | MEMORY CIRCUITS AND METHOD FOR ACCESSING DATA OF THE MEMORY CIRCUITS - A memory circuit includes at least one first memory cell of a first memory array for storing a first datum. The at least one first memory cell is coupled with a first word line and a first bit line. A first bit line bar is disposed substantially parallel with the first bit line. A first switch is coupled between a sense amplifier and the first bit line bar. The first switch can electrically isolate the sense amplifier from the first bit line bar if the sense amplifier is capable of sensing a first voltage difference between the first bit line. The first bit line bar and the first voltage difference is substantially equal to or larger than a predetermined value. | 03-24-2011 |
20120032511 | VSS-SENSING AMPLIFIER - Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line. | 02-09-2012 |
20120039143 | SENSE AMPLIFIER WITH ADJUSTABLE BACK BIAS - A circuit having a sensing circuit and at least one of a first node and a second node is described. The sensing circuit includes a pair of a first type transistors and a pair of a second type transistors. Each transistor of the pair of the first type transistors is coupled in series with a transistor of the pair of the second type transistors. The first node has a first voltage and is coupled to each bulk of each transistor of the pair of the first type transistors. The second node has a second voltage and is coupled to each bulk of each transistor of the pair of the second type transistors. | 02-16-2012 |
20120243359 | SENSE AMPLIFIER - A circuit comprises a first node, a second node, a sense amplifier, at least one first transistor, at least one second transistor, and one or a combination of a first control circuit and a second control circuit. The first control circuit is configured to generate a first control signal for at least one first gate of the at least one first transistor. The first control signal is capable of having a first voltage level lower than a first operational voltage. The second control circuit is configured to generate a second control signal for at least one second gate of the at least one second transistor. The second control signal is capable of having a second voltage level higher than a second operational voltage. | 09-27-2012 |
20120256681 | CHARGE PUMP - A charge pump circuit comprises a first node, a second node, and at least one capacitance stage coupled between the first node and the second node. Capacitance stages of the at least one capacitance stage are coupled in series. A capacitance stage of the at least one capacitance stage includes a capacitive device and a voltage limiter coupled in parallel with the capacitor. The voltage limiter is configured to limit a voltage dropped across the capacitor. The capacitive device and the voltage limiter are configured such that a first current flowing through a first branch having the voltage limiter is more than a second current flowing through a second branch having the capacitive device. | 10-11-2012 |
20120275242 | VSS-SENSING AMPLIFIER - Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line. | 11-01-2012 |
20120307580 | PRE-CHARGE AND EQUALIZATION DEVICES - A circuit comprises a set of pre-charge and equalization devices, a control signal line, and a word line. The set of pre-charge and equalization devices is configured to pre-charge and equalize a pair of data lines. The control signal line is configured to control the pre-charge and equalization devices. The word line is configured to electrically couple a memory cell to a data line of the pair of data lines. A first voltage value provided to the control signal line is from a first voltage source different from a second voltage source that generates a second voltage value for the word line. | 12-06-2012 |
20130010561 | SENSE AMPLIFIERS AND EXEMPLARY APPLICATIONS - Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed. | 01-10-2013 |
20130135946 | DUAL RAIL MEMORY ARCHITECTURE - A memory macro comprises a plurality of memory cells, a plurality of first amplifying circuits, a first driver circuit, and a first level shifter. The plurality of memory cells is arranged in groups of a first direction and groups of a second direction. Each amplifying circuit is coupled to a plurality of first memory cells arranged in a first group of the first direction via a first data line. The first driver circuit is configured to drive the plurality of first amplifying circuits. The first level shifter is configured to level shift an input signal operating in a first power domain to an output signal operating in a second power domain. The output signal of the first level shifter is for use by the first driver circuit. The first driver circuit and a sense amplifier of an amplifying circuit operate in the second power domain. | 05-30-2013 |
20130170313 | WORDLINE DRIVER - A circuit includes a first transistor and a second transistor of a first type. The circuit further includes a first transistor of a second type. A first first-type drain is coupled to a second first-type source. A first first-type source is configured to have a first voltage value. A first first-type gate is configured to have a first control signal. A second first-type drain is configured to serve as a wordline. A second first-type gate is configured to have a second voltage value. A first second-type source is configured to have a third voltage value. A first second-type gate is configured to have a second control signal. The first transistor and the second transistor of the first type are configured to provide the first voltage value for the wordline. The first transistor of the second-type is configured to provide the third voltage value the wordline. | 07-04-2013 |
20130223174 | BOOSTING SUPPLY VOLTAGE - A data split between a first data line and a second data line is caused to develop. At least one of the following sets of steps is performed: 1) a first power supply line of a sense amplifier is caused to rise towards a first power supply voltage value, and when the first power supply line reaches a first predetermined voltage value, the first power supply is caused to rise above the first power supply voltage value; and 2) a second power supply line of the sense amplifier is caused to fall towards a second power supply voltage value, and when the second power supply line reaches a second predetermined voltage value, the second power supply line is caused to fall below the second power supply voltage value. | 08-29-2013 |
20140078844 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ACCESSING THE MEMORY CIRCUITS - A sense amplifier includes a first transistor. The first transistor includes a gate connected to a bit line, and a first source/drain (S/D) electrically coupled with a global bit line. The sense amplifier further includes a second transistor. The second transistor includes a gate connected to a first signal line, and a first S/D coupled to the global bit line, wherein the second transistor is configured to pre-charge the bit line. | 03-20-2014 |
20140119135 | MEMORY ARCHITECTURE - A first current value flowing through a transistor coupled with a storage node of a memory cell is determined when the transistor is off. A second current value flowing through the transistor is determined when the transistor is in on. A first reference voltage value at a reference node of the memory cell when the transistor is off is higher than a second reference voltage value at the reference node when the transistor is on. Based on the first current value, the second current value, and a relationship between the first current value and the second current value, a number of memory cells to be coupled with a data line associated with the memory cell is determined. | 05-01-2014 |
20140119138 | MEMORY ARCHITECTURE - A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit. | 05-01-2014 |
20140241077 | TRACKING CIRCUIT - A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined. | 08-28-2014 |
20140241087 | SENSE AMPLIFIER - A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage. | 08-28-2014 |
20140269023 | BIASING BULK OF A TRANSISTOR - A circuit comprises a first transistor of a first type, a second transistor of a second type, and a third transistor of the first type or the second type. The first transistor and the second transistor form an inverter. The third transistor is coupled with an output of the inverter. The circuit includes at least one of the following voltage sources: a first voltage source, a second voltage source, and a third voltage source. The first voltage source is coupled with a bulk of the first transistor, and is different from a first supply voltage source of the first transistor. T second voltage source is coupled with a bulk of the second transistor, and is different from a second supply voltage of the second transistor. The third voltage source is coupled with a bulk of the third transistor. | 09-18-2014 |
20140282332 | FAULT INJECTION OF FINFET DEVICES - Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures. | 09-18-2014 |
20140354346 | POWER MANAGEMENT DURING WAKEUP - A circuit comprises a first set of first transistors and a second set of transistors. The first transistors are configured to be turned on in a sequential manner. The second transistors are configured to be turned on in a sequential manner after the first transistors are turned on. A transistor of the first set of first transistors corresponds to a first time delay. The first set of first transistors corresponds to a second time delay that is a multiple of the first time delay. | 12-04-2014 |
20150078110 | READ TRACKING MECHANISM - A read time tracking mechanism (RTTM) for ensuring sufficient read time is provided. The read time tracking mechanism includes a read tracking circuit, which includes a tracking bit line (TBL) tracking circuit with one or more tracking cells, and a tracking word line (TWL). The RTTM also includes a sense amplifier enable (SAE) timing device configured to change the logic threshold of tracking WL (TWL) to delay the timing of signal change of TWL when necessary to ensure sufficient read time. The read time tracking mechanism is used to provide sufficient read time for memory arrays with various configurations, prepared under various process conditions, and operated under various voltages, and temperatures. | 03-19-2015 |
20150138903 | WRITING TO MULTI-PORT MEMORIES - A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port. | 05-21-2015 |
20150143315 | FAULT INJECTION OF FINFET DEVICES - A device layout tool includes a gate electrode layer, wherein the gate electrode layer is configured to define a three dimensional gate structure over a fin structure, wherein the fin structure has three exposed surfaces. The device layout tool further includes a defect-describing layer, wherein the defect-describing layer is configured to define locations of gate defects relative to the three exposed surfaces of the fin structure. | 05-21-2015 |
20150146470 | WRITE ASSIST CIRCUIT FOR WRITE DISTURBED MEMORY CELL - A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed. | 05-28-2015 |
20150228331 | CLAMPING CIRCUIT FOR MULTIPLE-PORT MEMORY CELL - A circuit includes a memory cell, a first data line, a second data line, and a clamping unit. The memory cell includes a data node, a first pass gate, and a second pass gate. The first pass gate is between the first data line and the data node. The second pass gate is between the second data line and the data node. The clamping unit is electrically coupled to the first data line and configured to pull a voltage level of the first data line toward a clamped voltage level when the clamping unit is enabled, and to function as an open circuit to the first data line when the clamping unit is disabled. The clamping unit is disabled when a first control signal indicates that a voltage level of the second data line is pulled toward a reference voltage level. | 08-13-2015 |
20150302938 | DETECTING WRITE DISTURB IN MULTI-PORT MEMORIES - A circuit comprises a memory cell, a first circuit, and a second circuit. The memory cell has a first control line and a second control line. The first control line carries a first control signal. The second control line carries a second control signal. The first circuit is coupled with the first control line, the second control line, and a node. The second circuit is coupled to the node and is configured to receive a first clock signal and a second clock signal. The first circuit and the second circuit, based on the first control signal, the second control signal, the first clock signal and the second clock signal, are configured to generate a node signal on the node. A logical value of the node signal indicates a write disturb condition of the memory cell. | 10-22-2015 |
Patent application number | Description | Published |
20080207536 | Antibacterial Agents - The present invention provides acylide derivatives, which can be used as antibacterial agents. Compounds disclosed herein can be used for the treatment or prevention of a condition caused by or contributed to by Gram-positive, Gram-negative or anaerobic bacteria, more particularly against bacterium such as | 08-28-2008 |
20080287376 | Ketolide Derivatives as Antibacterial Agents - The present invention provides ketolide derivatives, which can be used as antibacterial agents. In particular, compounds described herein can be used for treating or preventing conditions caused by or contributed to by Gram-positive, Gram-negative or anaerobic bacteria, more particularly against, for example, Staphylococci, Streptococci, Enterococci, | 11-20-2008 |
20090005325 | Ketolide Derivatives as Antibacterial Agents - Provided herein are ketolide derivatives, which can be used as antibacterial agents. Compounds described herein can be used for treating or preventing conditions caused by or contributed to by gram positive, gram negative or anaerobic bacteria, more particularly against, for example, | 01-01-2009 |
20090170790 | KETOLIDE DERIVATIVES AS ANTIBACTERIAL AGENTS - The present invention provides ketolide derivatives, which can be used as anti-bacterial agents. Compounds disclosed herein can be used for the treating or preventing conditions caused by or contributed to by gram positive, gram negative or anaerobic bacteria, more particularly against, for example, | 07-02-2009 |
20090215764 | Antimicrobial agents - Provided herein are substituted aromatic compounds, which are tRNA synthetase inhibitors, and hence can be used as antimicrobial agents. Compounds described herein can be used for the treatment or prevention of a condition caused by or contributed to by gram positive, gram negative, anaerobic bacteria or fungal organisms, more particularly against bacterium, for example, | 08-27-2009 |