Yu-Ling
Yu-Ling Chang, Kaohsiung City TW
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20150200292 | FLASH MEMORY STRUCTURE AND METHOD FOR FORMING THE SAME - Embodiments of mechanisms of a semiconductor structure are provided. The semiconductor device structure includes a substrate and a floating gate having a first sidewall and a second sidewall formed over the substrate. The semiconductor device further includes an insulating layer formed over the substrate to cover the first sidewall and an upper portion of the second sidewall of the floating gate. The semiconductor device further includes a control gate formed over the insulating layer. In addition, the floating gate is formed in a shark's fin shape. | 07-16-2015 |
Yu-Ling Cheng, Tainan City TW
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20150118408 | WET COATING METHOD - A wet coating method is described, which includes the following steps. A film coating is applied to at least one surface of a substrate using a wet process. A plasma-assisted filling treatment is performed on the film coating to crystallize the film coating into a film. The plasma-assisted filling treatment includes using a filling coating. | 04-30-2015 |
Yu-Ling Cheng, New Taipei City CN
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20140233786 | GRILLE ATTACHMENT FOR LOUDSPEAKER - A grille attachment for a loudspeaker is disclosed. A grille retainer is defined by a retention lip portion, a radial rim interface portion, and a hinge portion. The radial rim interface portion is in an abutting relationship with a flange radial mounting surface of the loudspeaker basket. The hinge portion connects the retention lip portion and the radial rim interface portion. The retention lip portion extends toward a flanged rim of the speaker basket, and defines an inner retention surface that is opposed to a flange circumferential surface. A grille extends across the griller retainer and is defined by a grille body and a grille rim that is circumferentially disposed and extending from the grille body. The grille rim is interposed between the flange circumferential surface and the inner retention surface, with the retention lip portion exerting a radial compressive force against the grille rim. | 08-21-2014 |
Yu-Ling Hsieh, New Taipei City TW
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20140246223 | SUBSTRATE - The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package. | 09-04-2014 |
Yu-Ling Hsieh, Xindian City TW
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20110299259 | CIRCUIT BOARD WITH CONDUCTOR POST STRUCTURE - Various circuit board interconnect conductor structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is disclosed that includes forming a conductor post on a side of a circuit board. The conductor post includes an end projecting away from the side of the circuit board. A solder mask is applied to the side of the circuit board to cover the conductor post. A thickness of the solder mask is reduced so that a portion of the conductor post projects beyond the solder mask. | 12-08-2011 |
20130062786 | SOLDER MASK WITH ANCHOR STRUCTURES - Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site. | 03-14-2013 |
Yu-Ling Hsu, Tainan City TW
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20140151782 | Methods and Apparatus for Non-Volatile Memory Cells with Increased Programming Efficiency - Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided. | 06-05-2014 |
20150021679 | Architecture to Improve Cell Size for Compact Array of Split Gate Flash Cell with Buried Common Source Structure - Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head. | 01-22-2015 |
20160035736 | High Endurance Non-Volatile Memory Cell - The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor. | 02-04-2016 |
Yu-Ling Hsu, Taipei City TW
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20150146285 | REFLECTIVE STRUCTURE FOR OPTICAL TOUCH SENSING - A reflective structure for optical touch sensing, which includes a transparent substrate, a plurality of microstructures and a transmittive reflective layer. The transparent substrate has a surface. The microstructures are disposed on the transparent substrate and expose a portion of the surface to allow a visible light to pass through. The transmittive reflective layer is disposed on the microstructures and at least covers a portion of the microstructures. | 05-28-2015 |
Yu-Ling Huang, Hsinchu City TW
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20130171634 | BIOMARKERS FOR CANCERS RESPONSIVE TO MODULATORS OF HEC1 ACTIVITY - Contemplated compositions and methods are drawn to biomarkers and methods related to treatment of neoplastic disease with Hec1 inhibitor. Gene status and/or expression levels of Hec1(HEC), Rb(RB1), and/or p53 (TP53) may be useful as biomarkers for sensitivity to treatment with a Hec1 inhibitor. In addition, Hec 1 inhibitors may show synergistic effects when used in conjunction with cytotoxic drugs. | 07-04-2013 |
20130190312 | MODULATORS OF HEC1 ACTIVITY AND METHODS THEREFOR - Compounds, compositions, and methods for modulation of Hec1/Nek2 interaction are provided. Such compounds disrupt Nek2/Hec1 binding and may be useful as chemotherapeutic agents for neoplastic diseases. | 07-25-2013 |
20150250794 | MODULATORS OF HEC1 ACTIVITY AND METHODS THEREFOR - Compounds, compositions, and methods for modulation of Hec1/Nek2 interaction are provided. Such compounds disrupt Nek2/Hec1 binding and may be useful as chemotherapeutic agents for neoplastic diseases. | 09-10-2015 |
Yu-Ling Huang, Taichung City TW
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20130157454 | SELF-ALIGNED WET ETCHING PROCESS - A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators. | 06-20-2013 |
20130193511 | VERTICAL TRANSISTOR STRUCTURE - A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation. | 08-01-2013 |
20130234230 | Semiconductor Device and Method for Making the Same - A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches. | 09-12-2013 |
Yu-Ling Kao, Kweishang TW
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20090008258 | Porous catalyst structure and its manufacturing method - A porous catalyst structure with a high specific surface area comprising a porous substrate with a catalyst layer thereon is provided. The porous catalyst structure can be prepared by a process comprising depositing a metallic layer onto the surface of a porous, metallic substrate by electroplating, and optionally oxidizing the metallic layer into the metal oxide layer. Any conductive porous metallic substrate can be used as the substrate of the subject invention, and the metallic layer may comprise any suitable metal(s) and/or metal oxide(s) with desired catalytic function(s). | 01-08-2009 |
20110064631 | HYDROGEN GENERATOR AND THE APPLICATION OF THE SAME - A hydrogen generator essentially composed of a first medium is provided, comprising: a reforming zone, a preheating zone and a heat source. The reforming zone is used for containing a reforming catalyst so as to perform a steam reforming reaction of a hydrogen-producing raw material to generate hydrogen; and the heat source provides heat to the preheating zone and reforming zone, so that the hydrogen-producing raw material is firstly preheated in the preheating zone and then performs the steam reforming reaction in the reforming zone. The reforming zone and preheating zone are divided with a shortest interval of at least about 0.5 mm with the first medium, wherein the first medium has a thermal conductivity (K) of at least about 60 W/m-K. | 03-17-2011 |
Yu-Ling Kuo, Hsichih KR
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20100142159 | Securing Device, and Assembly of an Electronic Device and the Securing Device - In an assembly of an electronic device having one side provided with at least one securing hole, and a securing device including a body, an abutting and retaining member, and a guiding unit, the body includes a base for placement of the electronic device thereon, and a lateral plate extending upwardly from one side of the base and having an inner side formed with at least one protrusion for engaging the securing hole. The abutting and retaining member is movably and slidably disposed on the base opposite to the lateral plate. The guiding unit is connected to the abutting and retaining member and the base for guiding displacement of the abutting and retaining member so that the latter is rotatable relative to the base to abut against the other side of the electronic device when being displaced from a release position to a securing position. | 06-10-2010 |
Yu-Ling Kuo, Taipei TW
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20090091901 | ELECTRONIC DEVICE - An electronic device. The electronic device comprises housing, a positioning member and a circuit board. The positioning member, disposed on the housing, comprises a first protruding portion. The circuit board engages with the positioning member. The first protruding portion is a resilient member contacting with the circuit board to constrain the circuit board between the first protruding portion and the housing by an elastic force. | 04-09-2009 |
Yu-Ling Kuo, Hsichih TW
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20090268412 | Housing For An Electronic Device - A housing for an electronic device includes a housing body with a front panel and an outer peripheral panel. A cover is coupled to the housing body, is located in front of the front panel, and is formed with an opening. A locking mechanism includes an actuating member disposed in the opening, a transmitting member coupled to the actuating member and disposed on a rear face of the cover, and a rod member disposed on the rear face of the cover. The transmitting member has a catch portion disposed to be retained at the front panel, and an arm portion. The actuating member drives the transmitting member to rotate such that the catch portion is retained at the front panel and the arm portion pushes one end of the rod member to move, thereby enabling the other end of the rod member to be retained at the outer peripheral panel. | 10-29-2009 |
Yu-Ling Kuo, New Taipei City TW
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20120138444 | BUTTON MECHANISM AND ELECTRONIC DEVICE THEREWITH - A button mechanism includes a circuit structure and an actuating structure. The circuit structure includes a substrate, a first electrode layer, and a second electrode layer. The first electrode layer and the second electrode layer are disposed on the substrate, and the second electrode layer is separated from the first electrode layer. The first electrode layer includes a first section and a second section. The second electrode layer includes a third section and a fourth section. The second section stretches to the third section, and the fourth section stretches to the first section. A predetermined gap is formed between the first electrode layer and the second electrode layer, and the predetermined gap includes a plurality of curved portions. The actuating structure includes a conductive portion for conducting the first electrode layer and the second electrode layer. | 06-07-2012 |
20120233928 | DOOR STRUCTURE WITH EASY ASSEMBLY - A door structure includes a handle whereon an engaging part, a sunken part, and a baffle part disposed nearby the sunken part are formed. The door structure further includes a cover connected to the handle. The cover includes a main body, a hook disposed on a side of the main body, a rib disposed on the side of the main body for installing inside the sunken part, and a protruding part disposed on the side of the main body for blocking the baffle part so as to fix the handle on the cover with the hook and the rib. | 09-20-2012 |
20140139981 | DOOR STRUCTURE WITH EASY ASSEMBLY AND ELECTRONIC DEVICE THEREWITH - A door structure includes a rotary cover, a pivotal portion and a shielding component. The rotary cover is connected to a housing in a rotatable manner. The rotary cover covers a slot on the housing as rotating to a closed position. The pivotal portion is connected to the rotary cover and passes through a pivoting hole on the housing to be pivoted on the housing so that the rotary cover is capable of rotating relative to the housing. The shielding component is installed on the pivotal portion and disposed inside the housing. The shielding component is for shielding at least one part of the pivoting hole on the housing when the rotary cover rotates to an open position to expose the slot on the housing and the shielding component pivots to a position corresponding to or nearby the pivoting hole with the pivotal portion. | 05-22-2014 |
20140139982 | DISPLAY DEVICE CAPABLE OF FIXING A SCREEN AT DIFFERENT VIEW ANGLES - The present invention discloses a display device including a base, a screen and a fixing mechanism. The fixing mechanism is connected to the base and the screen for fixing the screen on the base. The fixing mechanism includes a supporting structure rotatably installed on the base. Two ends of the supporting structure selectively engage with a plurality of constraining portions on the screen so as to fix the screen at different view angles relative to the base. The fixing mechanism further includes a resilient component sheathing with the supporting structure. An end of the resilient component is fixed on the base, and the other end of the resilient component is fixed on the supporting structure. The resilient component provides torque to the supporting structure as the screen rotates relative to the base. | 05-22-2014 |
20150185412 | LIGHT SOURCE MODULE - A light source module including a light guide and a light source is provided. An end of the light guide has a light incident surface, and the other end of the light guide has at least three light-guiding branches. The light-guiding branches respectively extend along different extending directions and each light-guiding branch has a light emitting surface. The light source is adapted for providing a light beam, wherein the light beam enters the light guide through the light incident surface and the light beam exits the light guide from the light emitting surfaces. | 07-02-2015 |
Yu-Ling Lee, Hsinchu TW
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20150364844 | ELECTRONIC CARD PROTECTING MECHANISM - An electronic card protecting mechanism is adapted to an electronic device including a casing. The electronic card protecting mechanism includes a base, a substrate, an elastic component and a positioning component. The base is slidably disposed in the casing and has a covering plate having a slot. The substrate is disposed on the base and aligned to the slot. When the base is located at a first position, an opening of the casing is covered by the covering plate. When the base resists an elastic force of the elastic component and moves to a second position, the positioning component positions the base and the opening is aligned to the slot, such that the electronic card is adapted to be plugged to or unplugged from the substrate through the opening. When the base is released by the positioning component, the base is restored by the elastic force of the elastic component. | 12-17-2015 |
Yu-Ling Li, Chung-Li TW
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20110184696 | Detection and Analysis Apparatus For Membrane Filtration Process - The present invention discloses a detection and analysis apparatus, comprising a photo sensing device, comprising a plurality of sensing elements linearly arranged to form a first array, for detecting a signal of the thickness change of the cake at a linear position of the filter medium; a driving device, for driving the photo sensing device to move relatively parallel to the filter medium on the top of the cake so that the photo sensing device detects the thickness change of the cake on at least one local plane of the filter medium; and a data processing device, coupling to the photo sensing device, for continuously processing and analyzing the signal detected by the photo sensing device to thereby in-situ estimate the thickness change of the cake on the at least one local plane of the filter medium during the filtration process. | 07-28-2011 |
Yu-Ling Li, New Taipei City TW
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20150321146 | COMPOSITE MEMBRANE UTILIZED IN MEMBRANE DISTILLATION - A composite membrane includes a hydrophobic porous membrane and a high water content hydrogel layer disposed on the surface of the hydrophobic porous membrane facing the hot end. The surface active agents contained in the wastewater at the hot end are blocked by the high water content hydrogel layer, thus the problem of pore wetting of the hydrophobic porous membrane can be prevented. Therefore, the membrane distillation technique can be utilized for processing wastewater containing surface active agents. | 11-12-2015 |
Yu-Ling Liang, Changhua County TW
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20120256275 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a metal gate structure includes first providing a substrate having a dummy gate formed thereon. The dummy gate includes a high-K gate dielectric layer, a bottom barrier layer, a first etch stop layer and a sacrificial layer sequentially and upwardly stacked on the substrate. Then, the sacrificial layer is removed to form a gate trench with the first etch stop layer exposed on the bottom of the gate trench. After forming the gate trench, a first work function metal layer is formed in the gate trench. | 10-11-2012 |
Yu-Ling Lin, Hsinchu TW
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20130115426 | METHOD OF MANUFACTURING FLEXIBLE ELECTRONIC DEVICE - A method for manufacturing a flexible electronic device includes forming a first layer on a substrate to define a first area and a second area surrounding the first area such that the substrate is exposed at least partially in the first area and the first layer is in the second area, forming a second layer on the first area and the first layer over the second area such that an adhesion force between the second layer and the substrate in the first area is weaker than that between the second and first layers in the second area, forming an electronic device layer (EDL) on the second layer over the first area, the EDL defining a boundary projectively within the first area, and separating the EDL from the substrate by cutting through the first and second layers along a contour within the first area but not less than the boundary. | 05-09-2013 |
Yu-Ling Lin, Taipei 112 TW
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20130147023 | INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE - The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps. | 06-13-2013 |
Yu-Ling Lin, Hsinchu City TW
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20130329415 | LIGHT EMITTING MODULE - A light emitting module includes a substrate, two first LEDs (light emitting diode), two second LEDs (light emitting diode) and at least one first circular LED array. The substrate includes a first central line and a second central line. The first central line and the second central line are substantially perpendicularly crossed on the center of the substrate. The first LEDs are disposed oppositely on the first central line and spatially separated by the center of the substrate. The second LEDs are disposed oppositely on the second central line and spatially separated by the center of the substrate. The color temperature of the light emitted by the first LEDs is different from which by the second LEDs. The first circular LED array is disposed on the substrate. | 12-12-2013 |
Yu-Ling Lin, Beitou District Taipei TW
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20140264745 | Transmission Line Formed Adjacent Seal Ring - An integrated circuit device includes a semiconductor body, active components formed over the semiconductor body, one or more seal rings surrounding the active components, and a signal line. One or more of the seal rings are configured to provide the primary return path for current flowing through the signal line. | 09-18-2014 |
20150325517 | Structure And Method For A High-K Transformer With Capacitive Coupling - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer. | 11-12-2015 |
Yu-Ling Lin, Taipei TW
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20100238000 | System and Method for Persistent ID Flag for RFID Applications - A system and method for persistent ID flag for RFID applications includes a method for operating an RFID tag. The method includes measuring a voltage potential of a supply voltage for the RFID tag, and turning on a pass gate that couples a memory cell to a data line used for reading or writing data, if the voltage potential is greater than a first threshold. An accumulated charge on the memory cell is also measured, and both the voltage potential and the accumulated charge are used to generate a control signal to set a state of the pass gate. The pass gate is turned off if the control signal is a true value. | 09-23-2010 |
20120092230 | ON-CHIP HELIX ANTENNA - A rectangular helix antenna in an integrated circuit includes upper electrodes disposed in a first metal layer, lower electrodes disposed in a second metal layer, and side electrodes connecting the upper electrodes with the lower electrodes, respectively. The upper electrodes are disposed at an angle with respect to the lower electrodes. The upper electrodes, the lower electrodes, and the side electrodes form one continuous electrode spiraling around an inner shape of a rectangular bar. A micro-electromechanical system (MEMS) helix antenna has a similar structure to the rectangular helix antenna, but can have an inner shape of a bar. | 04-19-2012 |
20120104575 | Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes - A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips. | 05-03-2012 |
20120133446 | Quadrature Voltage Controlled Oscillator Including Transmission Line - A circuit includes an oscillator circuit including a first oscillator and a second oscillator. The first and the second oscillators are configured to generate signal having a same frequency and different phases. A transmission line is coupled between the first and the second oscillators. | 05-31-2012 |
20120146680 | DE-EMBEDDING ON-WAFER DEVICES - A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed. | 06-14-2012 |
20120146741 | TRANSFORMER WITH BYPASS CAPACITOR - An electronic device comprises first, second and third inductors connected in series and formed in a metal layer over a semiconductor substrate. The first and second inductors have a mutual inductance with each other. The second and third inductors having a mutual inductance with each other. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first and second inductors. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second and third inductors. | 06-14-2012 |
20120153433 | Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps - A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump. | 06-21-2012 |
20120268229 | Compact Vertical Inductors Extending in Vertical Planes - A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor. | 10-25-2012 |
20120299778 | ANTENNA USING THROUGH-SILICON VIA - An antenna includes a substrate and a top plate disposed over the substrate. At least one feed line is connected to the top plate, and each feed line comprises a first through-silicon via (TSV) structure passing through the substrate. At least one ground line is connected to the top plate, and each ground line comprises a second TSV structure passing through the substrate. The top plate is electrically conductive, and the at least one feed line is arranged to carry a radio frequency signal. The at least one ground line is arranged to be coupled to a ground. | 11-29-2012 |
20130032799 | Apparatus and Methods for De-Embedding Through Substrate Vias - A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs. | 02-07-2013 |
20130099352 | STRUCTURE AND METHOD FOR A HIGH-K TRANSFORMER WITH CAPACITIVE COUPLING - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer. | 04-25-2013 |
20130134553 | INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES - Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise. | 05-30-2013 |
20130154053 | INDUCTORS WITH THROUGH VIAS - A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate. | 06-20-2013 |
20130168809 | STRUCTURE AND METHOD FOR A TRANSFORMER WITH MAGNETIC FEATURES - The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors. | 07-04-2013 |
20130200447 | Adjustable Meander Line Resistor - An adjustable meander line resistor comprises a plurality of series circuits. Each series circuit comprises a first resistor formed on a first doped region of a transistor, a second resistor formed on a second doped region of the transistor and a connector coupled between the first resistor and the second resistor. A control circuit is employed to control the on and off of the transistor so as to achieve the adjustable meander line resistor. | 08-08-2013 |
20130200448 | Meander Line Resistor Structure - A meander line resistor structure comprises a first resistor formed on a first active region, wherein the first resistor is formed by a plurality of first vias connected in series, a second resistor formed on a second active region, wherein the second resistor is formed by a plurality of second vias connected in series and a third resistor formed on the second active region, wherein the third resistor is formed by a plurality of third vias connected in series. The meander line resistor further comprises a first connector coupled between the first resistor and the second resistor. | 08-08-2013 |
20130228894 | STRUCTURE AND METHOD FOR A FISHBONE DIFFERENTIAL CAPACITOR - The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material. | 09-05-2013 |
20130234305 | 3D TRANSMISSION LINES FOR SEMICONDUCTORS - A transmission line structure for semiconductor RF and wireless circuits, and method for forming the same. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground plane, and a second die including a second substrate, a second insulating layer, and a signal transmission line. The second die may be positioned above and spaced apart from the first die. An underfill is disposed between the ground plane of the first die and the signal transmission line of the second die. Collectively, the ground plane and transmission line of the first and second die and underfill forms a compact transmission line structure. In some embodiments, the transmission line structure may be used for microwave applications. | 09-12-2013 |
20130246990 | SYSTEM AND METHOD FOR MODELING THROUGH SILICON VIA - A computer implemented system comprises a processor programmed to analyze a circuit to determine a response of the circuit to an input radio frequency (RF) signal, for at least one of designing, manufacturing, and testing the circuit. An interposer model is tangibly embodied in a non-transitory machine readable storage medium to be accessed by the processor. The interposer model is processed by the computer to output data representing a response of a though substrate via (TSV) to the radio frequency (RF) signal. The interposer model comprises a plurality of TSV models. Each TSV model has a respective three-port network. One of the ports of each three-port network is a floating node. The floating nodes of each of the three-port networks are connected to each other. | 09-19-2013 |
20130277794 | Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps - A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump. | 10-24-2013 |
20140001609 | INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES | 01-02-2014 |
20140008773 | Integrated Antenna Structure - Some embodiments relate to a semiconductor module comprising an integrated antenna structure configured to wirelessly transmit signals. The integrated antenna structure has a lower metal layer and an upper metal layer. The lower metal layer is disposed on a lower die and is connected to a ground terminal. The upper metal layer is disposed on an upper die and is connected to a signal generator configured to generate a signal to be wirelessly transmitted. The upper die is stacked on the lower die and is connected to the lower die by way of an adhesion layer having one or more micro-bumps. By connecting the lower and upper die together by way of the adhesion layer, the lower and upper metal layers are separated from each other by a large spacing that provides for a good performance of the integrated antenna structure. | 01-09-2014 |
20140041173 | TRANSFORMER WITH BYPASS CAPACITOR - An electronic device comprises first, second and third inductors connected in series and formed in a metal layer over a semiconductor substrate. The first and second inductors have a mutual inductance with each other. The second and third inductors having a mutual inductance with each other. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first and second inductors. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second and third inductors. | 02-13-2014 |
20140070366 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided. | 03-13-2014 |
20140097930 | Structure and Method for a Transformer with Magnetic Features - The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors. | 04-10-2014 |
20140117501 | DIFFERENTIAL MOSCAP DEVICE - A differential MOS capacitor structure includes two capacitor sections coupled to different gates and operating using different signals. The respective signals may be 180° out of phase. The capacitor sections of the differential capacitor each include two or more upper capacitor plates disposed over a single common lower capacitor plate which serves as a common node thereby preventing parasitic capacitance. The upper capacitor plates of a first capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates of a second capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates are formed of a plurality of stacked conductive layers in some embodiments. | 05-01-2014 |
20140152512 | ANTENNA USING THROUGH-SILICON VIA - An antenna includes a substrate and a conductive top plate over the substrate. A feed line is connected to the top plate, and the feed line comprises a first through-silicon via (TSV) structure passing through the substrate. The feed line is arranged to carry a radio frequency signal. A method of designing an antenna includes selecting a shape of a top plate, determining a size of the top plate based on an intended signal frequency, and determining, based on the shape of the top plate, a location of each TSV of at least one TSV contacting the top plate. A method of implementing an antenna includes forming a first feed line through a substrate, the first feed line comprising a TSV, and forming a top plate over the substrate, the top plate being electrically conductive and connected to the first feed line. | 06-05-2014 |
20140203397 | Methods and Apparatus for Inductors and Transformers in Packages - Methods and apparatus for forming a semiconductor device package with inductors and transformers using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top die and a bottom die, or between a die and an interposer. An inductor can be formed by a redistribution layer within a bottom device and a micro-bump line above the bottom device connected to the RDL. The inductor may be a symmetric inductor, a spiral inductor, a helical inductor which is a vertical structure, or a meander inductor. A pair of inductors with micro-bump lines can form a transformer. | 07-24-2014 |
20140211438 | Methods and Apparatus for Transmission Lines in Packages - Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes. | 07-31-2014 |
20140327005 | Apparatus and Methods for De-Embedding Through Substrate Vias - An apparatus for de-embedding through substrate vias is provided. The apparatus may include pads on a first side of a substrate are coupled to through vias extending through a substrate, wherein pairs of the through vias are interconnected by transmission lines of varying lengths along a second side of the substrate. The apparatus may further include pairs of pads coupled together by transmission lines of the same varying lengths. Apparatuses may include through vias surrounding a through via device under test. The surrounding through vias are connected to the through via device under test by a backside metal layer. The apparatus may further include a dummy structure having an area equal to an area of the backside metal layer. | 11-06-2014 |
20150031184 | METHODS OF MANUFACTURING A PACKAGE - A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line. | 01-29-2015 |
20150048432 | Meander Line Resistor Structure - A system comprises a first transistor comprising a first active region and a second active region, a first resistor comprising a plurality of first vias connected in series, wherein the first resistor is over the first active region, a second resistor comprising a plurality of second vias connected in series, wherein the second resistor is over the second active region, a second transistor comprising a third active region and a fourth active region, a capacitor having a terminal electrically coupled to the fourth active region and a bit line electrically coupled to the third active region. | 02-19-2015 |
20150050789 | Meander Line Resistor Structure - A method comprises implanting ions in a substrate to form a first active region and a second active region, depositing a first dielectric layer over the substrate, forming a first via and a second via in the first dielectric layer, wherein the first via is over the first active region and the second via is over the second active region, depositing a second dielectric layer over the first dielectric layer, forming a third via and a fourth via in the second dielectric layer, wherein the third via is over the first via and the fourth via is over the second via and forming a connector in a metallization layer over the second dielectric layer, wherein the connector is electrically connected to the third via and the fourth via. | 02-19-2015 |
20150123244 | DIFFERENTIAL MOSCAP DEVICE - A differential MOS capacitor includes a first plurality of upper capacitor plates, a second plurality of upper capacitor plates, and a conductive plate. At least two of the second plurality of upper capacitor plates are spaced laterally from each other and are disposed laterally between at least two of the first plurality of upper capacitor plates. The conductive plate is configured to serve as a common bottom capacitor plate such that a first capacitor is formed by the first plurality of upper capacitor plates and the conductive plate and a second capacitor is formed by the second plurality of upper capacitor plates and the conductive plate. | 05-07-2015 |
20150255207 | STRUCTURE AND METHOD FOR A TRANSFORMER WITH MAGNETIC FEATURES - The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors. | 09-10-2015 |
20150316603 | De-Embedding On-Wafer Devices - An apparatus includes three components. The first component includes a first transmission line; the second component is coupled with the first component and includes a second transmission line; and the third component electrically coupled with the first component and/or the second component. The transmission lines each include a substrate with a p-well or n-well within the substrate and a shielding layer over the p-well or n-well. The transmission lines also each include a plurality of intermediate conducting layers over the shielding layer, the plurality of intermediate conducting layers coupled by a plurality of vias. The transmission lines further each include a top conducting layer over the plurality of intermediate conducting layers. | 11-05-2015 |
20150325513 | Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes - A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips. | 11-12-2015 |
20160027750 | Methods and Apparatus for Transmission Lines in Packages - Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes. | 01-28-2016 |
20160035729 | Meander Line Resistor Structure - A system comprises a first transistor comprising a first drain/source region and a second drain/source region, a second transistor comprising a third drain/source region and a fourth drain/source region, wherein the first transistor and the second transistor are separated by an isolation region, a first resistor formed by at least two vias, wherein a bottom via of the first resistor is in direct contact with the first drain/source region, a second resistor formed by at least two vias, wherein a bottom via of the second resistor is in direct contact with the second drain/source region, a bit line connected to the third drain/source region through a plurality of bit line contacts and a capacitor connected to the fourth drain/source region through a capacitor contact. | 02-04-2016 |
20160049722 | ON-CHIP HELIX ANTENNA - An antenna includes a plurality of upper electrodes in a first metal layer, a plurality of lower electrodes in a second metal layer, a plurality of side electrodes connecting the upper electrodes with the lower electrodes, and a ground structure. The upper electrodes, the lower electrodes and the side electrodes form one continuous electrode. The continuous electrode extends in a first direction away from a reference plane over a substrate. The upper electrodes extend in a second direction different from the first direction. The upper electrodes, the lower electrodes, and the side electrodes are embedded within a waveguide structure that includes a dielectric material. The substrate has a length extending in the first direction greater than a length the continuous electrode extends in the first direction. The waveguide structure includes a portion of the substrate in a region beyond the length of the continuous electrode in the first direction. | 02-18-2016 |
20160071805 | INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES - Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise. | 03-10-2016 |
Yu-Ling Lin, Tainan City TW
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20150328183 | PHARMACEUTICAL COMPOSITION AND USE FOR APPLYING 7,7''-DIMETHOXYAGASTISFLAVONE IN INHIBITING TUMOR METASTASIS - A pharmaceutical composition for inhibiting tumor metastasis is disclosed. The pharmaceutical composition includes a therapeutically effective amount of 7,7″-Dimethoxyagastisflavone (DMGF) and a pharmaceutically acceptable carrier. The present invention also discloses a use of DMGF for manufacturing a pharmaceutical composition applied to inhibit tumor metastasis. The application of the pharmaceutical composition and the use of the present invention are advantageous for inhibiting tumor metastasis efficiently. | 11-19-2015 |
Yu-Ling Lu, Taipei City TW
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20130007669 | SYSTEM AND METHOD FOR EDITING INTERACTIVE THREE-DIMENSION MULTIMEDIA, AND ONLINE EDITING AND EXCHANGING ARCHITECTURE AND METHOD THEREOF - A system and method are provided to edit interactive three-dimensional multimedia. A user interface of the system is provided with an event level template that includes event series levels with multiple event developing points. Through the user interface, multiple interactive events related to a first character of the event developing point are edited. Through a three-dimensional engine, interactive relevances are built up between interactive events and multiple materials inside one or more database. When the interactive three-dimensional multimedia with multiple materials is output, the interactive events corresponding to the event developing points are performed according to a user command. An online editing and exchanging method integrated with the system and method is also provided to share pre-edited templates on an exchange server; each of the pre-edited templates is extracted from an interactive three-dimensional multimedia pre-edited by the system and method. | 01-03-2013 |
Yu-Ling Tsai, Hsinchu TW
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20130127040 | DIE CARRIER FOR PACKAGE ON PACKAGE ASSEMBLY - A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package. | 05-23-2013 |
Yu-Ling Tseng, New Taipei City TW
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20160087166 | LED LUMINOUS STRUCTURE FOR BACKLIGHT SOURCE - Disclosed is an LED luminous structure for backlight source with good light emitting efficiency and color light rendering and capable of preventing oxidation or affects overall light quality. The LED luminous structure includes a base, a blue LED chip, a green LED chip, a red phosphor and an encapsulation. The blue and green LED chips are installed on the base, and the red phosphor absorbs is excited by a light emitted from the blue LED chip to produce a red light. The encapsulation is for packaging the aforementioned components. The red phosphor has a particle size of 20-30 μm, and the encapsulation has a moisture permeability of 10-20 g/m | 03-24-2016 |
Yu-Ling Wu, Taipei City TW
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20120071405 | COMPOSITION OF INHIBITING PATHOLOGICAL ANGIOGENESIS - The present invention provides a pharmaceutical composition for inhibiting pathologic angiogenesis and/or cell proliferative disorder. The pharmaceutical composition of the present invention comprises an effective amount of LECT2 protein or analogue thereof, and a pharmaceutically acceptable carrier. | 03-22-2012 |
Yu-Ling Yu, Taipei TW
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20140252548 | Filter and Capacitor Using Redistribution Layer and Micro Bump Layer - An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer. | 09-11-2014 |