Patent application number | Description | Published |
20090007031 | METHOD AND SYSTEM FOR IMPLEMENTING CACHED PARAMETERIZED CELLS - Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design. | 01-01-2009 |
20090113369 | REGISTRY FOR ELECTRONIC DESIGN AUTOMATION OF INTEGRATED CIRCUITS - A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application; saving the constraint identification values and the constraint relationship values in a constraint registry element; and providing an interface to a user for accessing values of the constraint registry element. | 04-30-2009 |
20090172624 | Method and System for Implementing Stacked Vias - The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical user interface (GUI) to interactively manipulate the element. | 07-02-2009 |
20100115207 | METHOD AND SYSTEM FOR IMPLEMENTING MULTIUSER CACHED PARAMETERIZED CELLS - An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counters). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data. | 05-06-2010 |
Patent application number | Description | Published |
20100004902 | SPINE SELECTION MODE FOR LAYOUT EDITING - Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a single interconnect layer, of the same width, and collectively arranged such that the spine has a first end and a second end, and can be traced from the first end to the second end without backtracking. | 01-07-2010 |
20110066995 | ANNOTATION MANAGEMENT FOR HIERARCHICAL DESIGNS OF INTEGRATED CIRCUITS - A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating the annotation with the mirrored block hierarchy in computer readable storage media. | 03-17-2011 |
20120030644 | METHOD AND SYSTEM FOR IMPLEMENTING STACKED VIAS - The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical user interface (GUI) to interactively manipulate the element. | 02-02-2012 |