Ramamurthy
Ramamurthy Badrinath, Bangalore Karnataka IN
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20120005307 | STORAGE VIRTUALIZATION - A method of providing access to a plurality of different file systems implemented across a plurality of storage spaces comprises receiving a request for at least one storage space. The method further comprises receiving a request for at least one storage space and processing the request based at least in part on one of a location metadata and a file metadata, the location metadata including attributes associated with the plurality of storage spaces and the file metadata including attributes associated with one or more files stored at the plurality of storage spaces. | 01-05-2012 |
Ramamurthy Chandhrasekhar, Cupertino, CA US
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20120320558 | Electromagnetic Shielding Structures for Selectively Shielding Components on a Substrate - Electronic components on a substrate may be shielded using electromagnetic shielding structures. Insulating materials may be used to provide structural support and to help prevent electrical shorting between conductive materials and the components. The shielding structures may include compartments formed using metal fences that surround selected components or by injection molding plastic. The shielding structures may be formed using metal foil wrapped over the components and the substrate. Electronic components may be tested using test posts or traces to identify components that are faulty. The test posts or traces may be deposited on the substrate and may be used to convey test signals between test equipment and the components. After successful testing, the test posts may be permanently shielded. Alternatively, temporary shielding structures may be used to allow testing of individual components before an electronic device is fully assembled. | 12-20-2012 |
Ramamurthy Kasula, Nellore IN
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20110151258 | PREPARATION OF RANOLAZINE - Preparation of ranolazine and intermediates thereof, for use in pharmaceutical compositions comprising ranolazine. | 06-23-2011 |
Ramamurthy Katikareddy, Andhra Pradesh IN
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20100197732 | Repaglinide Substantially Free of Dimer Impurity - The present invention provides highly pure repaglinide substantially free of dimer impurity, and process for the preparation thereof. The present invention also relates to 2-ethoxy-N-[(1S)-3-methyl-1-[2-(1-piperidinyl)phenyl]butyl]-4-[2-[[(1S)-3-methyl-1-[2-(1-piperidinyl)phenyl]butyl]amino]-2-oxoethyl]benzamide, an impurity of repaglinide, and a process for preparing and isolating thereof. The present invention further relates to pharmaceutical compositions comprising solid particles of pure repaglinide substantially free of dimer impurity or pharmaceutically acceptable salts thereof, wherein 90 volume-percent of the particles (D | 08-05-2010 |
Ramamurthy Krithivas, Austin, TX US
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20090006832 | Method and System for linking Firmware Modules in a Pre-Memory Execution Environment - A BIOS includes a core and multiple modules. The modules include both those that are platform specific and those that are not platform specific. Each module has a standard interface that allows the core (or other module) to call the module. A platform vendor constructs a BIOS by selecting modules from one or more vendors, which when executed can select modules that are suitable for the platform the BIOS resides in. | 01-01-2009 |
Ramamurthy Krithivas, Chandler, AZ US
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20140006764 | METHODS, SYSTEMS AND APPARATUS TO IMPROVE SYSTEM BOOT SPEED | 01-02-2014 |
20140189197 | SHARING SERIAL PERIPHERAL INTERFACE FLASH MEMORY IN A MULTI-NODE SERVER SYSTEM ON CHIP PLATFORM ENVIRONMENT - Methods and apparatus related to sharing Serial Peripheral Interface (SPI) flash memory in a multi-node server SoC (System on Chip) platform environment are described. In one embodiment, multi-port non-volatile memory is shared by a plurality of System on Chip (SoC) devices. Each of the plurality of SoC devices comprises controller logic to control access to the multi-port non-volatile memory and/or to translate a host referenced address of a memory access request to a linear address space and a physical address space of the multi-port non-volatile memory. Other embodiments are also disclosed and claimed. | 07-03-2014 |
Ramamurthy Narayan, Oxford GB
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20090247623 | DERIVATIVES OF EPIRUBICIN, THEIR MEDICINAL APPLICATION AND PHARMACEUTICALY ACCEPTABLE FORMS OF DRUGS - The present invention relates to novel derivatives of epirubicin, pharmaceutical composition comprising these derivatives, and uses of epirubicin and its derivative for treating HCV. | 10-01-2009 |
Ramamurthy Vishweshwara, Bangalore IN
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20090125858 | IC Design Flow Incorporating Optimal Assumptions of Power Supply Voltage Drops at Cells when Performing Timing Analysis - An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which the output of a cell is expected to switch, and performing timing analysis based on the selected values. By using appropriate smaller sub-intervals within the timing window, more optimal physical layout of the design may be obtained. In an embodiment, the sub-intervals equal a cell delay, i.e., the delay between an input change to an output change for the corresponding cell. According to another aspect of the present invention, the sub-interval for later cells in a timing path are modified based on modified timing window of previous cells in the path, to reduce the computational requirement. | 05-14-2009 |
Ramamurthy Vishweshwara, Jayanagar IN
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20130174104 | PLACEMENT AWARE CLOCK GATE CLONING AND FANOUT OPTIMIZATION - Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design. | 07-04-2013 |