Patent application number | Description | Published |
20100005666 | CHAIN LINK SHARPENING METHOD AND APPARATUS - Embodiments provide various components of a chain saw, including saw chain elements, sprockets, and other fixtures, that may facilitate sharpening of cutter links during operation. In various embodiments, the components may increase stability during sharpening, provide nose mounted sharpening fixtures, and/or facilitate the resizing and/or reshaping of a sharpening element. | 01-14-2010 |
20110030223 | BAR MOUNTED SHARPENER - Embodiments include a sharpening fixture adapted to mount to the nose of a chainsaw guide bar. When mounted, the operator may direct a force towards the guide bar thereby causing a linear directed actuator to move a sharpening element into engagement with cutters of a saw chain to sharpen a cutting edge of the cutters. In various embodiments, the actuator is biased such that when the force is no longer applied, the actuator pulls the sharpening element out of engagement with the cutters. | 02-10-2011 |
20120036725 | KICKBACK DETECTION METHOD AND APPARATUS - In various embodiments, a cutting tool such as a chainsaw may include a cutting member that is movable by an engine, one or more sensors configured to detect one or more of acceleration in a direction parallel to one or more axes of the cutting tool and rotational velocity about one or more axes of the cutting tool, and a microprocessor configured to cause movement of the cutting member to stop in response to receiving one or more signals from the one or more sensors. In various embodiments, a method may include receiving, by a microprocessor of a chainsaw, a signal from a gyroscope configured to detect rotational velocity about one or more axes of the cutting tool, and actuating, by the microprocessor, a braking system of the chainsaw to stop movement of a cutting chain around a perimeter of a guide bar in response to the signal. | 02-16-2012 |
20140054054 | BATTERY OPERATED TOOL - Embodiments provide methods, apparatuses, and systems for battery operated tools, such as chainsaws, are provided. In accordance with embodiments herein, a chainsaw may include various components, such as a control board having a controller, a battery terminal block, a motor, a brake switch, a trigger switch, and/or other components. In various embodiments, components of the battery operated tool are provided that improve the capabilities and/or operation of the tool. | 02-27-2014 |
Patent application number | Description | Published |
20090006757 | HIERARCHICAL CACHE TAG ARCHITECTURE - An apparatus, system, and method are disclosed. In one embodiment, the apparatus includes a cache memory coupled to a processor. The apparatus additionally includes a tag storage structure that is coupled to the cache memory. The tag storage structure can store a tag associated with a location in the cache memory. The apparatus additionally includes a cache of cache tags coupled to the processor. The cache of cache tags can store a smaller subset of the tags stored in the tag storage structure. | 01-01-2009 |
20100077140 | SCALABLE SCHEDULERS FOR MEMORY CONTROLLERS - Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a memory device in an optimal fashion, e.g., to maximize bandwidth and/or reduce latency. Other embodiments are also disclosed and claimed. | 03-25-2010 |
20100122046 | Memory Micro-Tiling - According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel. | 05-13-2010 |
20100165780 | DYNAMIC RANDOM ACCESS MEMORY WITH SHADOW WRITES - Methods and apparatus are disclosed for reducing write-to-read turnaround times using shadow writes in memory controllers and in DRAM. Embodiments of controllers including shadow write control logic may, in response to receiving a write request, issue an external write column address strobe (CAS) to DRAM to latch a valid write CAS address, and assert a set of write data values to be stored in a set of DRAM locations corresponding to the write CAS address. After asserting the write CAS and prior to asserting the complete set of write data values, such memory controllers may, in response to receiving a read request, issue an external read CAS to DRAM to indicate a valid read CAS address. A set of read data values from a second set of DRAM locations corresponding to the read CAS address, are received with reduced turnaround time after asserting the complete set of write data values. | 07-01-2010 |
20100202229 | METHOD AND APPARATUS FOR SELECTIVE DRAM PRECHARGE - Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed | 08-12-2010 |
20110153916 | HYBRID MEMORY ARCHITECTURES - Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system. | 06-23-2011 |
20120194989 | MEMORY SYSTEMS WITH MEMORY CHIPS DOWN AND UP - In some embodiments, a system includes a memory controller chip, memory chips on a first substrate, and a module connector. A first group of conductors is included to provide read data signals from at least some of the memory chips to the memory controller chip, and a second group of conductors to provide read data signals from the connector to the memory controller chip. The module connector may receive a continuity card or memory module. Other embodiments are described. | 08-02-2012 |
20120294101 | METHOD AND APPARATUS FOR SELECTIVE DRAM PRECHARGE - Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed | 11-22-2012 |
20130275664 | SCALABLE SCHEDULERS FOR MEMORY CONTROLLERS - Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a memory device in an optimal fashion, e.g., to maximize bandwidth and/or reduce latency. Other embodiments are also disclosed and claimed. | 10-17-2013 |
20130322556 | ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DUPLEX MODES - An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched. | 12-05-2013 |
20140009195 | MECHANISMS FOR CLOCK GATING - Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled. | 01-09-2014 |
20140201405 | INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE INPUT/OUTPUT INTERFACES - An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. | 07-17-2014 |