Patent application number | Description | Published |
20080197362 | SEMICONDUCTOR LED, OPTO-ELECTRONIC INTEGRATED CIRCUITS (OEIC), AND METHOD OF FABRICATING OEIC - A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section. | 08-21-2008 |
20080290401 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICES WITH CHARGE INJECTION CORNER - An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved. | 11-27-2008 |
20090014775 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. | 01-15-2009 |
20090052259 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device is provided. A gate electrode configuring a memory cell is turned into floating state and a potential of a gate electrode adjacent thereto is changed, and reduce the potential of the gate electrode by this change of potential and the capacitive coupling. Furthermore, charge sharing is carried out by connecting two gate electrodes, and the voltage of the gate electrode is reduced by capacitive coupling with another gate electrode adjacent thereto, to largely reduce the potential of the gate electrode. Thereby, the voltage level generated by the charge pump circuit can be reduced. As a result, the size of the charge pump circuit can be reduced, or the circuit itself can be eliminated, resulting in reduction of the chip area. | 02-26-2009 |
20090122609 | SEMICONDUCTOR DEVICE - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section. | 05-14-2009 |
20090132974 | METHOD FOR SEMICONDUCTOR CIRCUIT - Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain. | 05-21-2009 |
20090134449 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n | 05-28-2009 |
20090152619 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down. | 06-18-2009 |
20090231921 | MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - In a nonvolatile semiconductor storage device having a split-gate memory cell including a control gate electrode and a sidewall memory gate electrode and a single-gate memory cell including a single memory gate electrode on the same silicon substrate, the control gate electrode is formed in a first region via a control gate insulating film, the sidewall memory gate electrode is formed in the first region via a charge trapping film, and at the same time, a single memory gate electrode is formed in a second region via the charge trapping film. At this time, the sidewall memory gate electrode and the single memory gate electrode are formed in the same process, and the control gate electrode and the sidewall memory gate electrode are formed so as to be adjacently disposed to each other in a state of being electrically isolated from each other. | 09-17-2009 |
20090261412 | Semiconductor Device and Manufacturing Method of the Same - A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI. | 10-22-2009 |
20090273014 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Each of a memory gate, a control gate, a source diffusion layer, and a drain diffusion layer is connected to a control circuit for controlling potential, and the control circuit operates so as to supply a first potential to the memory gate, a second potential to the control gate, a third potential to the drain diffusion layer, and a fourth potential to the source diffusion layer. Here, after setting the memory gate to be in a floating state by shifting a switch transistor from an ON state to an OFF state, the control circuit operates so as to supply a sixth potential which is higher than the second potential to the control gate to make the memory gate have a fifth potential which is higher than the first potential, thereby boosting the memory gate. | 11-05-2009 |
20090309153 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A process of forming a non-volatile memory in a memory region on a silicon substrate, in which a select gate electrode is formed on a main surface of the silicon substrate, and a dummy gate adjacent to one of sidewall surfaces of the electrode is formed. Then, memory source/drain regions are formed by ion implantation using the dummy gate as an ion implantation mask. Then, the dummy gate is removed, and a charge accumulating film and a memory gate electrode are sequentially formed at the part where the dummy gate has been provided, thereby forming a structure in which the memory source/drain regions are arranged at portions below and lateral to the memory gate electrode. In this process, the charge accumulating film and the memory gate electrode are formed after the ion implantation for forming the memory source/drain regions is carried out. | 12-17-2009 |
20100038700 | Semiconductor Device - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section. | 02-18-2010 |
20100105199 | NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING EMBEDDED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SIDEWALL GATE - A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation. | 04-29-2010 |
20100135080 | FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other. | 06-03-2010 |
20100203697 | INTEGRATED SEMICONDUCTOR NONVOLATILE STORAGE DEVICE - An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. | 08-12-2010 |
20100232231 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. | 09-16-2010 |
20100261327 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n | 10-14-2010 |
20110001179 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a non-volatile memory in which charge is injected from a gate electrode to a charge accumulating layer, charge injection efficiency, charge retention characteristic and reliability are all improved compared with a conventional gate structure. In a nonvolatile memory which carries out write/erasure by changing the total charge amount by injecting electrons and holes into a silicon nitride film which makes up a charge accumulating layer, in order to highly efficiently carry out charge injection from a gate electrode, the gate electrode of a memory cell is made up of a two-layer film of a non-doped polysilicon layer and a metal material electrode layer. | 01-06-2011 |
20110039385 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film. | 02-17-2011 |
20110242888 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap. | 10-06-2011 |
20120026798 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. | 02-02-2012 |
20120086070 | FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other. | 04-12-2012 |
20120217513 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility. | 08-30-2012 |
20120287959 | GERMANIUM LIGHT-EMITTING ELEMENT - A germanium light-emitting device emitting light at high efficiency is provided by using germanium of small threading dislocation density. A germanium laser diode having a high quality germanium light-emitting layer is attained by using germanium formed over silicon dioxide. A germanium laser diode having a carrier density higher than the carrier density limit that can be injected by existent n-type germanium can be provided using silicon as an n-type electrode. | 11-15-2012 |
20130065368 | NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING EMBEDDED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SIDEWALL GATE - A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation. | 03-14-2013 |
20130146897 | 4h-SiC SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely. | 06-13-2013 |
20130228845 | FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other. | 09-05-2013 |
20130234236 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p | 09-12-2013 |
20130328062 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - In a MOSFET using a SiC substrate, a source region having low resistance and high injection efficiency is formed without performing a high-temperature heat treatment. | 12-12-2013 |
20130341729 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage. | 12-26-2013 |
20140327066 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p | 11-06-2014 |