Patent application number | Description | Published |
20090003429 | Apparatus And Method For Processing A Bitstream - Method and apparatus for processing a first bitstream are provided. The apparatus comprises an extraction unit and a generation unit. The extraction unit extracts an NAL unit from the first bitstream. The generation unit, coupled to the extraction unit, receives the NAL unit to generate a second bitstream according to the NAL unit. The second bitstream comprises a piece of information related to the NAL unit. The method comprises the steps of extracting an NAL unit from the first bitstream and generating a second bitstream comprising a piece of information related to the NAL unit. | 01-01-2009 |
20090251341 | HUFFMAN DECODING METHOD AND APPARATUS - A decoder for decoding an input bit stream into a plurality of symbols is provided. The decoder includes an extractor, a length generator, a base selector, and a processing unit. The extractor receives the input bit stream and extracts a code with a predetermined codeword length therefrom. The length generator receives the extracted code and determines a first codeword length corresponding to a symbol according to the extracted code and a base table. The base selector determines a codeword base corresponding to the first codeword length according to the base table. The processing unit generates the symbol corresponding to the extracted code according to the codeword base, an offset table and the first codeword length. | 10-08-2009 |
20090316775 | VIDEO ENCODING AND DECODING METHOD AND SYSTEM THEREOF - A video encoding system for encoding at least one frame, which includes a plurality of data units, to a bit stream. The system includes: a scaling unit, for scaling a data unit of a current frame to generate a scaled data unit in a first mode; and a video encoder, coupled to the scaling unit, for directly retrieving the scaled data unit from the scaling unit and encoding the scaled data unit to generate a coded data unit in the first mode. | 12-24-2009 |
20100034288 | VIDEO DECODING METHOD AND SYSTEM THEREOF - A video decoding method for decoding a bit stream to a plurality of frames, includes: determining whether a size of a current picture is equal to that of a next picture according to the bit stream; scaling a corresponding reference frame for the next picture to generate a scaled frame when the size of the current picture is not equal to that of the next picture; and storing the scaled frame in a first frame buffer of a storage unit, wherein at least a portion of a first frame originally stored in the first frame buffer is displayed. | 02-11-2010 |
20100079315 | HUFFMAN DECODING METHOD AND APPARATUS - A decoder for decoding an input bit stream into a plurality of symbols is provided. The decoder includes an extractor, a length generator, a base selector, and a processing unit. The extractor receives the input bit stream and extracts a code with a predetermined codeword length therefrom. The length generator receives the extracted code and determines a first codeword length corresponding to a symbol according to the extracted code and a base table. The base selector determines a codeword base corresponding to the first codeword length according to the base table. The processing unit generates the symbol corresponding to the extracted code according to the codeword base, an offset table and the first codeword length. | 04-01-2010 |
20100232517 | Method and Apparatus for Processing a Multimedia Bitstream - A method and apparatus for processing a multimedia bitstream are provided. The apparatus comprises a receive module, an extraction module, and a generation module. The receiving module receives the multimedia bitstream, wherein the multimedia bitstream comprises a plurality of NAL units. The extraction module extracts the NAL units from the multimedia bitstream. The generation module generates a processed bitstream comprising markers and NAL units. Each of the markers has a unique code. By doing so in future processing, a decoder or a decoding method can locate NAL units easily by searching for the corresponding marker. | 09-16-2010 |
20140297995 | FAULT-TOLERANT SYSTEM AND FAULT-TOLERANT OPERATING METHOD - A fault-tolerant system including a calculation unit and an output synthesizer is provided. The calculation unit receives a first environmental parameter and input data, wherein the calculation unit further includes a first and a second calculation circuits. The first calculation circuit is arranged to perform a calculation on the input data in response to the first environmental parameter to generate a first calculation result. The second calculation circuit is different from the first calculation circuit, and arranged to perform the calculation on the input data in response to the first environmental parameter to generate a second calculation result. The output synthesizer selects a first and a second set of bits from the first and the second calculation result according to a control signal, and synthesizes the first set of bits and the second set of bits in sequence to generate an adjusted calculation result. | 10-02-2014 |
Patent application number | Description | Published |
20120098006 | LIGHT EMITTING DIODE PACKAGE WITH PHOTORESIST REFLECTOR AND METHOD OF MANUFACTURING - Optical emitters are fabricated by forming and shaping photoresist reflectors on a package wafer using lithography processes, and bonding Light-Emitting Diode (LED) dies to the package wafer. | 04-26-2012 |
20120104450 | LIGHT EMITTING DIODE OPTICAL EMITTER WITH TRANSPARENT ELECTRICAL CONNECTORS - An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching. | 05-03-2012 |
20120244652 | METHODS OF FABRICATING LIGHT EMITTING DIODE DEVICES - An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor. | 09-27-2012 |
20120305956 | LED PHOSPHOR PATTERNING - The present disclosure provides a method of patterning a phosphor layer on a light emitting diode (LED) emitter. The method includes providing at least one LED emitter disposed on a substrate; forming a polymer layer over the at least one LED emitter; providing a mask over the polymer layer and the at least one LED emitter; etching the polymer layer through the mask to expose the at least one LED emitter within a cavity having polymer layer walls; and coating the at least one LED emitter with phosphor. | 12-06-2012 |
20140093990 | Light Emitting Diode Optical Emitter with Transparent Electrical Connectors - An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching. | 04-03-2014 |
20140252380 | Shadow Mask Assembly - A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly. | 09-11-2014 |
Patent application number | Description | Published |
20110101435 | BURIED BIT LINE PROCESS AND SCHEME - The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer. | 05-05-2011 |
20110147853 | Method of Forming an Electrical Fuse and a Metal Gate Transistor and the Related Electrical Fuse - The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor. | 06-23-2011 |
20120225524 | METHOD OF FORMING AN ELECTRICAL FUSE AND A METAL GATE TRANSISTOR AND THE RELATED ELECTRICAL FUSE - The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor. | 09-06-2012 |
20120228718 | METHOD OF FORMING AN ELECTRICAL FUSE AND A METAL GATE TRANSISTOR AND THE RELATED ELECTRICAL FUSE - The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor. | 09-13-2012 |
20130102829 | METHOD FOR TREATING OSTEOSARCOMA BY BORON NEUTRON CAPTURE THERAPY USING BORIC ACID AS A BORON DRUG - The present invention provides a treatment of osteosarcoma by boron neutron capture therapy using boric acid as a single boron drug. | 04-25-2013 |
20140065553 | CHUCK AND SEMICONDUCTOR PROCESS USING THE SAME - An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof. | 03-06-2014 |
20140113452 | WAFER EDGE TRIMMING METHOD - A wafer edge trimming method comprises steps as follows: Firstly, an etch-resistant layer is formed on a surface of a wafer. A wet treatment process is then performed to remove a portion of the etch-resistant layer, so as to expose a portion of the surface adjacent to an edge of the wafer. Subsequently, an etching process is performed to remove a portion of the wafer that is not covered by the remained etch-resistant layer. | 04-24-2014 |
Patent application number | Description | Published |
20090236583 | Method of fabricating a phase change memory and phase change memory - The present invention relates to a phase change memory and a method of fabricating a phase change memory. The phase change memory includes a heater structure disposed on a phase change material pattern, wherein the heater structure is in a tapered shape with a bottom portion contacting the phase change material pattern. The fabrication of the phase change memory is compatible with the fabrication of logic devices, and accordingly an embedded phase change memory can be fabricated. | 09-24-2009 |
20100012916 | PHASE CHANGE MEMORY - A phase change memory and the method for manufacturing the same are disclosed. The phase change memory includes a word line, a phase change element, a plurality of heating parts, and a plurality of bit lines. The phase change material layer is electrically connected to the word line and the heating parts. Each heating part is electrically connected to a respective bit line. | 01-21-2010 |
20100133649 | Contact efuse structure, method of making a contact efuse device containing the same, and method of making a read only memory containing the same - A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and thus the contact is open. Such structure may be utilized in an efuse device or a read only memory. A method of making a contact efuse device and a method of making a read only memory are also disclosed. | 06-03-2010 |
20100148915 | ELECTRICAL FUSE STRUCTURE AND METHOD FOR FABRICATING THE SAME - An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element. | 06-17-2010 |
20110117710 | METHOD OF FABRICATING EFUSE, RESISTOR AND TRANSISTOR - A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess. | 05-19-2011 |
Patent application number | Description | Published |
20110157082 | Matrix Resistive Touch Panel and Design Method Thereof - A matrix resistive touch panel including a plurality of first sensing electrodes, a plurality of second sensing electrodes, a control circuit and a compensating circuit is provided. Each first sensing electrode has a first end and a second end. Each second sensing electrode has a third end and a fourth end. The compensating circuit is electrically connected to the control circuit, the first and the second ends of the first sensing electrodes, and the third and the fourth ends of the second sensing electrodes. The compensating circuit is used for equating a plurality of first impedances between the first ends and the control circuit, equating a plurality of second impedances between the second ends and the control circuit, equating a plurality of third impedances between the third ends and the control circuit, and equating a plurality of fourth impedances between the fourth ends and the control circuit. | 06-30-2011 |
20110244640 | METHOD OF MANUFACTURING FLASH MEMORY CELL - A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively. | 10-06-2011 |
20120075218 | TOUCH PANEL AND TOUCH DISPLAY DEVICE USING THE SAME - A touch panel comprising a substrate, a touch element, a first grounding electrode, an insulation layer and a second grounding electrode is disclosed. The touch element is disposed on a first surface of the substrate. The first grounding electrode is disposed on the first surface to surround the touch element. The insulation layer is disposed on the first surface to cover the touch element and the first grounding electrode. The second grounding electrode is disposed on the first insulation layer or on a second surface of the substrate opposite to the first surface. Therefore, the ESD can be conducted to the grounding end G of the circuit component through the enclosed first grounding electrode, and the signal interference between the touch panel and display can be shielded by the second grounding electrode to enhance anti-ESD and anti-noise abilities of the touch panel. | 03-29-2012 |
20130062780 | CHIP STACKING STRUCTURE - A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process. | 03-14-2013 |
20130140688 | Through Silicon Via and Method of Manufacturing the Same - The present invention discloses a through silicon via and method of manufacturing the same comprising the steps of providing a substrate, forming a plurality of through silicon via (TSV) holes in said substrate, forming a seed layer on the surface of said substrate and said a plurality of TSV holes, forming a patterned mask on said substrate, wherein said patterned mask comprises a plurality of first openings corresponding to said TSV holes and a plurality of second openings adjacent to or surrounding said a plurality of first openings, forming a material layer on said substrate, wherein said material layer is filled into said TSV holes and said first openings to form a plurality of through silicon vias, and said material layer is filled into said second openings to form a plurality of dummy bumps. | 06-06-2013 |
20130140708 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized. | 06-06-2013 |
20130334669 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination. | 12-19-2013 |
20130334699 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes a substrate with a front side and a back side, an ILD, disposed on the substrate, a cap layer disposed on the backside of the substrate, a TSV penetrating the cap layer, the substrate and the ILD, wherein a cap layer sidewall in the TSV juts out beyond the substrate sidewall the TSV with a predetermined distance, and a liner is disposed on the substrate sidewall, wherein the liner partially overlaps with the cap layer. | 12-19-2013 |
20140106526 | METHOD OF MANUFACTURING FLASH MEMORY CELL - A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively. | 04-17-2014 |
20140145326 | SUBSTRATE WITH INTEGRATED PASSIVE DEVICES AND METHOD OF MANUFACTURING THE SAME - A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern. | 05-29-2014 |
20140203394 | Chip With Through Silicon Via Electrode And Method Of Forming The Same - The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening. | 07-24-2014 |
20140332952 | SEMICONDUCTOR STRUCTURE AND METHOD FOR TESTING THE SAME - A semiconductor structure comprising a substrate, a dielectric layer, a conductor post, a first conductive layer structure and a second conductive layer structure is provided. The substrate comprises an opening structure. The dielectric layer is disposed on a sidewall of the opening structure. The conductor structure is disposed in the opening structure and covers the dielectric layer. The first and second conductive layer structures are electrically connected to the conductor post. A voltage difference is existed between the first and second conductive layer structures, such that a current is passing through the first conductive layer structure, the opening structure and second conductive layer structure. A resistance values is related to the voltage difference and the current. A dimension of the opening structure is 10 times greater than a dimension of the first and second conductive layer structures. | 11-13-2014 |
20140346645 | THROUGH SILICON VIA AND PROCESS THEREOF - A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole. | 11-27-2014 |
20150014828 | Semiconductor Device Having Shielding Structure - The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connecting unit electrically connect a signal to the RF circuit. | 01-15-2015 |
20150061151 | PACKAGE STRUCTURE HAVING SILICON THROUGH VIAS CONNECTED TO GROUND POTENTIAL - A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding. | 03-05-2015 |
20150179516 | INTEGRATED STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure. | 06-25-2015 |
20150179580 | HYBRID INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating hybrid interconnect structure is disclosed. The method includes the steps of: providing a material layer; forming a through-silicon hole in the material layer; forming a patterned resist on the material layer, wherein the patterned resist comprises at least an opening for exposing the through-silicon hole; and forming a conductive layer to fill the through-silicon hole and the opening in the patterned resist. | 06-25-2015 |
Patent application number | Description | Published |
20120287976 | NETWORK DEVICE RELATING TO DIGITAL SUBSCRIBER LINE - A network device relating to a digital subscriber line (DSL) such as an asymmetrical DSL (ADSL) or a very high bit rate DSL (VDSL) is provided. In the present invention, the capacitors equipped into the network device are separated and grouped into two independent groups. When the network device runs out of power, the energy of one of the two independent groups is provided for generating the dying gasp signal, and the energy of the other of the two independent groups is provided for amplifying and transmitting the dying gasp signal to a Central Office (CO). Accordingly, the CO can be accurately known whether the network device runs out of power or not, and the respective capacitances of the two independent groups can be significantly reduced so as to reduce the cost of the network device. | 11-15-2012 |
20130217272 | USB 3.0 TWO-WAY SOCKET JACK CONNECTOR STRUCTURE - A USB 3.0 socket jack connector structure allows a USB plug connector to conduct working when it is plugged in the jack connector of the present invention positively or oppositely through a two-war sharing grounding transmission conductor, and a first signal transmission conductor, second signal transmission conductor, first differential signal transmission conductor, second differential signal transmission conductor, third grounding transmission conductor, third differential signal transmission conductor, fourth differential signal transmission conductor, first power supply transmission conductor, third signal transmission conductor, fourth signal transmission conductor, second power supply transmission conductor, fourth grounding transmission conductor, fifth differential signal transmission conductor, sixth differential signal transmission conductor, seventh differential signal transmission conductor and eighth differential signal transmission conductor. | 08-22-2013 |
20140102873 | Touch Panel Based Switch - A touch panel-based switch includes a control circuit layer, a sensing layer, a dielectric layer, and a touch operation layer, stacked in the order. The sensing layer electrically connected to the control circuit layer includes plural sensing cell, and the dielectric layer is flexible. The touch operation layer is flexible as well and includes a button area and an adjacent non-button area. The button area includes a ground plane stacked on the dielectric layer and a first touch cover stacked on the ground plane, and the non-button area includes a second touch cover stacked on the dielectric layer. Plural though openings are provided in the button area corresponding to the sensing cells such that a portion of the dielectric layer is exposed. | 04-17-2014 |
Patent application number | Description | Published |
20090091933 | KEYPAD ASSEMBLY AND PORTABLE ELECTRONIC DEVICE USING THE SAME - A keypad assembly ( | 04-09-2009 |
20090094790 | DOOR HINGE PIN FOR PORTABLE ELECTRONIC DEVICE - A door hinge pin ( | 04-16-2009 |
20090286431 | PROTECTIVE COVER MECHANISM - A protective cover mechanism ( | 11-19-2009 |
20090291363 | BATTERY COVER MECHANISM - A battery cover mechanism used in a portable electronic device includes a housing defining a receiving groove therein for receiving a battery, a cover mounted an elastic member, the elastic member defines a locking space, the housing has a protrusion formed thereon, the protrusion is latched with the locking space to latch the cover with the housing. | 11-26-2009 |
20100008607 | SLIDE MECHANISM FOR PORTABLE ELECTRONIC DEVICE - A slide mechanism includes a first plate and a second plate. The second plate includes a second main body, and two slide rails positioned on two end of the second main body. Each of the slide rails includes a rail portion and an embedded portion moldingly formed in the rail portion. The first plate is installed in the slide rails and slidable relative to the second plate. The invention also discloses a portable electronic device using the slide mechanism. | 01-14-2010 |
20100024304 | BATTERY COVER LATCH MECHANISM AND PORTABLE ELECTRONIC DEVICE USING SAME - A battery cover latch mechanism is configured for detachably assembling a battery cover on a housing. The battery cover latch mechanism includes a button, an assembly portion including two blocks positioned on the housing, a latching part positioned on the battery cover; and a resilient member secured on the button and latching to the blocks to provide a resilient force to the button. The button releasably latches to the latching part to lock the battery cover to the housing or release the battery cover from the housing. The invention also discloses a portable electronic device using the battery cover latch mechanism. | 02-04-2010 |
20110073452 | KEY BUTTON STRUCTURE - A key button structure includes a button body, a fixing member and a housing. The housing comprises a first housing and a second housing placed in the first housing. The first housing and the second housing together define an accommodating space. The first housing has a window defined therethrough communicating with the accommodating space. The fixing member and the button body are integrally and detachably assembled within the accommodating space of the housing. The button body is exposed through the window. | 03-31-2011 |
20110193828 | TELESCOPING STYLUS FOR PORTABLE ELECTRONIC DEVICE - A stylus includes a housing, a core, a pole and a positioning member. The core is slidably received in the housing. The pole is secured in the housing. The pole includes a first ring groove and a second ring groove. The positioning member is mounted to the core. A plurality of arcuate portions is formed on the positioning member. The arcuate portions are selectably engaged in the first ring groove and the second ring groove to position the stylus at different positions. | 08-11-2011 |
20110227880 | TELESCOPING STYLUS FOR PORTABLE ELECTRONIC DEVICE - A telescoping stylus includes a housing, a first stopper member, a second member, and a core member. The first stopper member is attached to one end of the housing. The second stopper member is attached to another end of the housing. The core member is slidably received in the housing. The core member selectively engages with the first stopper member or the second member to be positioned in the housing. | 09-22-2011 |
20110228493 | PROTECTIVE COVER, KEY ASSEMBLY USING THE SAME AND PORTABLE ELECTRONIC DEVICE USING THE KEY ASSEMBLY - A protective cover includes a cover body and a pressing body integrally mounted to the cover body. The cover body has an accommodating cavity recessed from a surface of the cover body and an accommodating hole defined through the base wall of the accommodating cavity. The pressing body is mounted to the cover body and includes a pressing portion and a resisting post. The pressing portion is configured for being received within the accommodating cavity and exposed from the accommodating hole. The resisting post protruding from a surface of the pressing portion away from the cover body corresponding to the switch. There also discloses a key assembly using the protective cover and a portable electronic device using the key assembly. | 09-22-2011 |