Patent application number | Description | Published |
20110280068 | JOINT ENCODING OF LOGICAL PAGES IN MULTI-PAGE MEMORY ARCHITECTURE - Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells. | 11-17-2011 |
20120075930 | REUSE OF INFORMATION FROM MEMORY READ OPERATIONS - A nominal reference read operation compares analog voltages of the memory cells to at least one nominal reference voltage. A shifted reference read operation compares the analog voltages of the memory cells to at least one shifted reference voltage that is shifted from the nominal reference voltage to compensate for an expected change in the analog voltages of the memory cells. Data stored in the memory cells is decoded by a first decoding process that uses the information from either the nominal reference read operation or the shifted reference read operation. The data stored in the memory cells is decoded by a second decoding process that uses the information from both the nominal reference read operation and the shifted reference read operation. | 03-29-2012 |
20120079355 | OPPORTUNISTIC DECODING IN MEMORY SYSTEMS - Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence. | 03-29-2012 |
20130007343 | Parameter Tracking for Memory Devices - Methods and systems involve collecting memory device parameters and using memory device parameters to determine memory wear information. A set of first parameters associated with wear of the memory device is monitored for at least one memory unit of the memory device. The first parameters are compared to respective trigger criterion. If the comparison reveals that one or more of the first parameters are beyond their trigger criterion, then collection of a second set of parameters is triggered. The second parameters are also indicative of the wear of the memory device. The set of first parameters may overlap the set of second parameters. The set of second parameters are used to develop memory wear information. In some implementations, the memory wear information may be configuration information used to configure the read/write channel to compensate for wear of the memory device. In some implementations, the memory wear information may be used to predict or estimate the lifetime of the device. | 01-03-2013 |
20150246476 | METHOD FOR FABRICATING RECTANGULAR PATTERED STACKS - The embodiments disclose an analyzer configured to determine positions of circumferential gratings track features and alignment patterns in a first template and a phase device configured to determine positions of radial gratings features and interspersed pattern fields in a second template, wherein the first template is transferred and cross-imprinted with the second template features and patterns to form a third template substrate as a rectangular patterned stack imprint template. | 09-03-2015 |
20150248914 | Skew Compensation in a Patterned Medium - Apparatus for providing skew compensation in a patterned medium, such as but not limited to a self-assembling bit patterned medium. In accordance with some embodiments, the apparatus includes a transducer and a rotatable substrate. The substrate has a plurality of rows of spaced apart data recording dots. Each row of dots is angularly offset from an immediately adjacent row responsive to a skew angle of the transducer. The rows of dots are arranged into concentric zones of hypertracks. Each zone has an arcuate timing field segment which extends across the zone and is angularly discontinuous with the timing field segment of an immediately adjacent zone. | 09-03-2015 |
Patent application number | Description | Published |
20110131444 | SYSTEMS AND METHODS FOR LOW WEAR OPERATION OF SOLID STATE MEMORY - This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability. | 06-02-2011 |
20110280069 | ITERATIVE DEMODULATION AND DECODING FOR MULTI-PAGE MEMORY ARCHITECTURE - Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each bit stored in a memory cell is associated with a page of data that is different from other pages associated with other bits stored in the memory cell. The multiple pages are demodulated responsive to sensed voltage levels of the memory cells, and a demodulated output is provided for each page of the multiple pages. A decoded output for each page of the multiple pages is generated. Decoding the page and demodulating the multiple pages proceeds iteratively, including an exchange of information between the decoder and the demodulator. | 11-17-2011 |
20110296272 | OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES - Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data. | 12-01-2011 |
20120278679 | Iterating Inner and Outer Codes for Data Recovery - A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable. | 11-01-2012 |
20140122975 | OPPORTUNISTIC DECODING IN MEMORY SYSTEMS - Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence. | 05-01-2014 |
Patent application number | Description | Published |
20100118424 | MEASUREMENT OF ROUND TRIP LATENCY IN WRITE AND READ PATHS - A method and apparatus for measuring latency in a communication path is provided. The technique includes driving a signal such as a square wave on the communication path, such as a write path such that it travels around the write-read path, and sensing a returned signal at one end of the write-read path. A square wave signal corresponding to the square wave driven on the write path is delayed by a predetermined phase thus generating a delayed signal. The returned signal and the delayed signal are mixed, producing a mixed signal. The mixed signal is integrated to obtain an integrated output. The phase by which the delayed signal is shifted is successively adjusted. Returned signals are mixed with such delayed signals until the integrated output is equal to zero. The phase shift amount that results in a nulled integrated output, less a quarter cycle of the square wave, is equal to the round trip latency of the write-read path. | 05-13-2010 |
20100118426 | WRITE CLOCK CONTROL SYSTEM FOR MEDIA PATTERN WRITE SYNCHRONIZATION - A write clock control system comprises a clock controller that determines a phase offset based on a phase difference between a write clock signal and a media pattern corresponding to a given timing synchronization field being read, and a phase interpolator that produces an updated write clock signal by updating the phase of the write clock signal in accordance with control signals that are based on the phase offset signal. | 05-13-2010 |
20100118427 | ELIMINATING SECTOR SYNCHRONIZATION FIELDS FOR BIT PATTERNED MEDIA - Clock synchronization techniques are described for data storage media, particularly for the tolerances of efficient use of bit patterned media (BPM) capacity. In particular, techniques are described where position of a read-write head and timing of a write and/or read clock is determined within a fraction of a dot of the underlying media. The techniques obviate the requirement for the fields conventionally written preceding a data sector to provide bit synchronization and symbol framing (sector synchronization fields). | 05-13-2010 |
20100118428 | INTERSPERSED PHASE-LOCKED LOOP FIELDS FOR DATA STORAGE MEDIA SYNCHRONIZATION - Techniques are described for providing media-referenced timing for operations on a data storage medium. In particular, Phase-Locked Loop (PLL) synchronization fields may be interspersed within data fields of the medium and may be read to obtain timing measurements. The PLL fields are illustratively pre-recorded at predetermined intervals on the medium and have a fixed number of dots of the bit patterned medium between the PLL fields. Phase and frequency of a write clock may be controlled based on the read PLL fields to translate the timing measurements from the PLL fields into phase and frequency corrections to synchronize the write clock to the data storage medium, | 05-13-2010 |
20100118429 | REDUCED READ/WRITE TRANSITION OVERHEAD FOR STORAGE MEDIA - A technique is described for reducing overhead in a magnetic medium utilizing interspersed timing synchronization fields. In particular, a reader reads timing synchronization fields interspersed within data fields of the medium to obtain timing measurements. The reader is separated from a writer by a distance greater than a distance of the reader to traverse a select timing synchronization field. As such, the writer may perform a direct current (DC) write to the medium to suspend transitional write operations while the reader is reading the select timing synchronization field, and/or while the writer is over a unipolar field (e.g., a timing synchronization field). | 05-13-2010 |
20100118433 | WRITE PRECOMPENSATION SYSTEM - A write precompensation system comprises a write precompensation processor that calculates time shift information for the timing of individual write current transitions at a write head to coincide with a media pattern under the write head and a write precompensation controller that shifts the individual write current transitions in accordance with the time shift information. | 05-13-2010 |
20100202079 | WRITE SYNCHRONIZATION PHASE CALIBRATION FOR STORAGE MEDIA - A technique is described for write synchronization phase calibration for storage media (e.g., bit patterned media). In one embodiment, a calibration write clock signal may be generated at a frequency offset from a nominal dot frequency of a bit patterned storage media. A periodic signal that was written to the media synchronous to the calibration write clock signal may then be read and mixed with a reference periodic signal at the nominal dot frequency to obtain a difference signal. This difference signal may be demodulated to determine a phase correction for write synchronization to the media. | 08-12-2010 |
20110231596 | Multi-Tiered Metadata Scheme for a Data Storage Array - Method and apparatus for managing metadata associated with a data storage array. In accordance with various embodiments, a group of user data blocks are stored to memory cells at a selected physical address of the array. A multi-tiered metadata scheme is used to generate metadata which describes the selected physical address of the user data blocks. The multi-tiered metadata scheme provides an upper tier metadata format adapted for groups of N user data blocks, and a lower tier metadata format adapted for groups of M user data blocks where M is less than N. The generated metadata is formatted in accordance with a selected one of the upper or lower tier metadata formats in relation to a total number of the user data blocks in the group. | 09-22-2011 |
20110252289 | ADJUSTING STORAGE DEVICE PARAMETERS BASED ON RELIABILITY SENSING - In general, this disclosure is directed to techniques for adjusting storage device parameters based on reliability sensing. According to one aspect, a method includes retrieving a codeword from a plurality of data blocks within a storage device, wherein each of the data blocks stores a respective portion of the codeword, generating a detected value for a bit within a first portion of the codeword based on information related to a reliability of a data block associated with the first portion, and performing error correction on a second portion of the codeword based on the detected value for the bit within the first portion of the codeword. According to another aspect, a method includes obtaining information related to a reliability of a data block within a storage device, and adjusting a data capacity for the storage device based on the information related to the reliability of the data block. | 10-13-2011 |
20110258380 | FAULT TOLERANT STORAGE CONSERVING MEMORY WRITES TO HOST WRITES - A data storage apparatus and associated method involving a memory with a plurality of storage elements defining an associated set of stored data, and memory control logic that, responsive to a request to store first data in a first storage element of the plurality of storage elements, computes without storing to any of the plurality of storage elements first redundancy data for the associated set of stored data inclusive of the first data. | 10-20-2011 |
20130124591 | RANDOM NUMBER GENERATION USING SWITCHING REGULATORS - Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data. | 05-16-2013 |
20130242428 | WRITE DELAY STABILIZATION - Apparatus and method for write delay stabilization. A write driver is adapted to output bipolar write currents to write data to a memory. A preconditioning circuit is adapted to output first and second thermal preconditioning currents through the write driver to stabilize a write delay associated with the write driver to a steady-state level prior to the writing of data to the memory. | 09-19-2013 |
20140016221 | PIN-EFFICIENT READER BIAS ENABLE CONTROL - Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write (RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal. | 01-16-2014 |
20140016222 | GAIN CONTROL FOR LATENCY TESTING - Approaches for determining the timing latency of a communication path are described. Some embodiments involve a method for testing timing latency. A signal is driven on a first data path and is returned through a second data path through a loop back element. The timing latency of at least a portion of the communication path that includes the first data path and the second data path is tested using the signal returned on the second data path. The gain of the second data path is adjusted to a test value during the testing of the timing latency. | 01-16-2014 |
20140029396 | HEAT ASSISTED MAGNETIC RECORDING DEVICE WITH PRE-HEATED WRITE ELEMENT - An apparatus includes a write element configured to apply a magnetic field to write data on a portion of a heat-assisted magnetic recording media in response to an energizing current. An energy source is configured to heat the portion of the media being magnetized by the write element. A preheat energizing current is applied to the write element during an interval before writing the data to the portion of the media. The preheat energizing current does not cause data to be written to the media and brings at least one of the write element and driver circuitry into thermal equilibrium prior to writing the data on the portion. | 01-30-2014 |
20140192435 | OFFSET CORRECTION VALUES ON A DATA STORAGE MEDIA - A memory system includes a storage medium having tracks arranged on the storage medium. The tracks include data track portions configured to store data. The tracks have a data track width and offset correction portions having a width that is greater than the data track width of the associated data track. Each offset correction portion stores one or both of positional offset correction values and timing offset correction values. The positional offset correction values are configured to correct for errors that occur in cross track positioning relative to the medium and the timing offset correction values are configured to correct for errors that occur in down track timing relative to the medium. | 07-10-2014 |
20150029613 | PIN-EFFICIENT READER BIAS ENABLE CONTROL - Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write (RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal. | 01-29-2015 |
20150074486 | TRANSFER UNIT MANAGEMENT - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a non-volatile memory is arranged into a plurality of blocks, with each of the blocks constituting an integral plural number N of fixed-sized, multi-bit transfer units. A processing circuit retrieves at least a portion of the data stored in a selected block to a volatile memory buffer in response to a transfer unit (TU) bit map. The TU bit map is stored in a memory and provides a multi-bit sequence of bits corresponding to the N transfer units of the selected block. The values of the bits in the multi-bit sequence of bits indicate whether the corresponding transfer units are to be retrieved. | 03-12-2015 |
20150074487 | Memory Device with Variable Code Rate - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location. | 03-12-2015 |
20150089278 | VARIABLE DATA RECOVERY SCHEME HIERARCHY - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines. | 03-26-2015 |
Patent application number | Description | Published |
20090177784 | END-POINT IDENTIFIERS IN SIP - A system and method for uniquely identifying an SIP device extends the SIP communications protocol with an end point identifier, carried for example in the header of an SIP transmission. The end point identifier is useful for routing, registration, subscription, and authentication. The end point (device) of a given user epid can be uniquely identified by creating a key from an epid and a user's address-of-record (URI). This in turn enables improved connection management and security association management when the connections/IP addresses are transient, such as when HTTPS tunneling is used. | 07-09-2009 |
20120084447 | End-Point Identifiers in SIP - A system and method for uniquely identifying an SIP device extends the SIP communications protocol with an end point identifier, carried for example in the header of an SIP transmission. The end point identifier is useful for routing, registration, subscription, and authentication. The end point (device) of a given user epid can be uniquely identified by creating a key from an epid and a user's address-of-record (URI). This in turn enables improved connection management and security association management when the connections/IP addresses are transient, such as when HTTPS tunneling is used. | 04-05-2012 |
20120324224 | STATELESS HUMAN DETECTION FOR REAL-TIME MESSAGING SYSTEMS - Stateless human detection for real-time systems allows a real-time message system to challenge incoming messages suspected of being generated by an automated application. When a suspect message is detected, a challenge is presented to a sender of the message. The challenge is designed to require human intervention to provide a correct answer to the challenge. A challenge packet is sent with the challenge and includes a challenge answer and, possibly, a server identifier, a challenge identifier and/or a time stamp that can be used to prevent attacks on the challenge. The challenge packet is encrypted so that the sender cannot access the contents thereof. When the sender provides a response to the challenge, the sender returns the challenge packet. The challenge packet is decrypted and the challenge answer is compared to a sender answer. If the answers match, the sender is allowed subsequent access to the messaging system. | 12-20-2012 |
20120324535 | STATELESS HUMAN DETECTION FOR REAL-TIME MESSAGING SYSTEMS - Stateless human detection for real-time systems allows a real-time message system to challenge incoming messages suspected of being generated by an automated application. When a suspect message is detected, a challenge is presented to a sender of the message. The challenge is designed to require human intervention to provide a correct answer to the challenge. A challenge packet is sent with the challenge and includes a challenge answer and, possibly, a server identifier, a challenge identifier and/or a time stamp that can be used to prevent attacks on the challenge. The challenge packet is encrypted so that the sender cannot access the contents thereof. When the sender provides a response to the challenge, the sender returns the challenge packet. The challenge packet is decrypted and the challenge answer is compared to a sender answer. If the answers match, the sender is allowed subsequent access to the messaging system. | 12-20-2012 |
20130036308 | END-TO-END AUTHENTICATION OF SESSION INITIATION PROTOCOL MESSAGES USING CERTIFICATES - End-to-end authentication capability based on public-key certificates is combined with the Session Initiation Protocol (SIP) to allow a SIP node that receives a SIP request message to authenticate the sender of request. The SIP request message is sent with a digital signature generated with a private key of the sender and may include a certificate of the sender. The SIP request message my also be encrypted with a public key of the recipient. After receiving the SIP request, the receiving SIP node obtains a certificate of the sender and authenticates the sender based on the digital signature. The digital signature may be included in an Authorization header of the SIP request, or in a multipart message body constructed according to the S/MIME standard. | 02-07-2013 |
20140040484 | END-POINT IDENTIFIERS IN SIP - A system and method for uniquely identifying an SIP device extends the SIP communications protocol with an end point identifier, carried for example in the header of an SIP transmission. The end point identifier is useful for routing, registration, subscription, and authentication. The end point (device) of a given user epid can be uniquely identified by creating a key from an epid and a user's address-of-record (URI). This in turn enables improved connection management and security association management when the connections/IP addresses are transient, such as when HTTPS tunneling is used. | 02-06-2014 |
20140044244 | VOICEMAIL SCREENING AND CALL RETRIEVAL - Handling an incoming call from a caller to a user includes prompting a caller to record a message to the user and sending a special command to a user communication device indicting that the incoming call is available for screening and retrieving. In response to the user indicating a desire to screen the incoming call, the user listens to the message while the caller is leaving the message. In response to the user indicating a desire to retrieve the incoming call, the call is transferred to the user communication device. In response to the user indicating a desire to screen the call, an incoming media stream from the incoming call may be forked so that the message is being recorded while the user is listening to the message at the user communication device. | 02-13-2014 |
Patent application number | Description | Published |
20090307533 | Activity Identifier Based Tracing and Troubleshooting - To trace an activity through multiple components or applications that may be involved in the performance of the activity, an activity identifier can be generated and utilized by the various components or applications. Each can generate its own activity identifier to minimize changes to existing interfaces. When logging of events has been activated, each application or component can provide, to an event store, an indication of the activity identifier it is using for a given activity. If a preceding or subsequent component utilizes a different activity identifier for aspects of the same activity, a link between the two activity identifiers can be communicated to the event store. Subsequently, examination of the event store can filter out irrelevant entries based on the activity identifiers. A graph linking the various related activity identifiers can be created and only those events associated with activity identifiers not in the graph can be filtered out. | 12-10-2009 |
20100223446 | CONTEXTUAL TRACING - A method of tracking execution of activities in a computing environment in which events in an activity are recorded along with an activity identifier uniquely identifying the activity and tying the events to the activity. To track interactions between activities, a correlation identifier may be generated and transferred between the interacting activities as part of the interaction. For each of the activities participating in the interaction, information on an event relating to the interaction is recorded along with the correlation identifier. The correlation identifier thus allows uniquely identifying each interaction which may be used to synchronize streams of events within the activities at points of their interaction. Activities may interact across any boundary, including a network. | 09-02-2010 |
20100229022 | COMMON TROUBLESHOOTING FRAMEWORK - Techniques for improving a troubleshooting experience by providing a common troubleshooting framework. Such a framework may enable use of common elements between troubleshooters and lead to similarities between troubleshooting packages, which may improve the user experience. Further, a framework may reduce the amount of knowledge and time necessary to create troubleshooting packages, and thus encourage increased development of these troubleshooting packages. In some implementations of the framework, a troubleshooting package may be implemented in a declarative manner that outlines/describes the problems it solves and the potential solutions to those problems. The declarative troubleshooting packages may then be provided to the troubleshooting framework and may provide direction to the framework, in that the framework may execute functions as directed by the troubleshooter. | 09-09-2010 |