Patent application number | Description | Published |
20080205163 | NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF - Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result. | 08-28-2008 |
20090003066 | Non-volatile memory system and programming method of the same - A programming method for a non-volatile memory system includes storing multi-page program data and buffering the multi-page program data from a page buffer to a memory block and programming the multi-page program data through a predetermined number of program operations. The programming the multi-page program data includes programming memory cells of the memory block using a first threshold voltage lower than a desired threshold voltage based on the multi-page program data sequentially buffered by the page buffer in units of pages and programming the memory cells using the desired threshold voltage by increasing a threshold voltage of the memory cells by a predetermined level at each successive program operation. | 01-01-2009 |
20090003067 | Non-volatile memory device for reducing layout area of global wordline decoder and operation method thereof - A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder. | 01-01-2009 |
20090052243 | Method of controlling a memory cell of non-volatile memory device - A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-volatile memory cells connected to bit lines corresponding to a second bit line group, second controlling data written to the non-volatile memory cells by varying a control voltage. The controlling may include reading or verifying. Before verification, the method may include writing data to the non-volatile memory cells. | 02-26-2009 |
20090091981 | NONVOLATILE MEMORY DEVICE WITH MULTIPLE PAGE REGIONS, AND METHODS OF READING AND PRECHARGING THE SAME - A nonvolatile memory device includes a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region configured with at least two adjacent memory cells coupled to the word line. The nonvolatile memory devices also includes a first common source line connecting with the memory cells of the first page region, and a second common source line connecting with the memory cells of the second page region. The first and second common source lines are controlled independently. | 04-09-2009 |
20090116296 | FLASH MEMORY DEVICE APPLYING ERASE VOLTAGE - A flash memory device includes; a plurality of layers, each one including memory cells arranged in a matrix of rows and columns, a layer decoder configured to select one of the plurality of layers to thereby define a selected layer and an unselected layer, a voltage generator configured to generate an erase voltage at a level higher than ground voltage, and an internal voltage, and a row select circuit configured to apply the erase voltage to the selected layer, and apply at least one of the erase voltage and the internal voltage to the unselected layer during an erase operation. | 05-07-2009 |
20090124072 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region. | 05-14-2009 |
20090135656 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH DUMMY CELLS AND METHOD OF PROGRAMMING THE SAME - A nonvolatile semiconductor memory device includes a memory cell array, an erase controller and a dummy cell controller. The memory cell array includes multiple cell strings, each including at least two dummy cells having different threshold voltages and normal memory cells. The erase controller performs, in cell block units, an erase operation for the normal memory cells of each cell string and an adjacent dummy cell of the at least two dummy cells positioned nearer the normal memory cells, and performs an erase verify operation for the normal memory cells. The dummy cell controller performs a program operation for each of the adjacent dummy cells within the memory cell array and a program verify operation of the adjacent dummy cells, and performs a program verify operation for remaining dummy cells, which are not adjacent dummy cells, and then a program operation for the remaining dummy cells requiring programming. | 05-28-2009 |
20090168482 | THREE-DIMENSIONAL MEMORY DEVICE - A three-dimensional memory device includes a base layer having a memory array and peripheral circuits formed on a bulk silicon substrate, and N circuit layers each having a memory array formed on a silicon-on-insulator (SOI) substrate. The N circuit layers are vertically stacked one on top of the other on the base layer and the uppermost Nth circuit layer additionally includes passive elements | 07-02-2009 |
20090168533 | THREE-DIMENSIONAL MEMORY DEVICE AND PROGRAMMING METHOD - A programming method and a three-dimensional memory device are disclosed. The three-dimensional memory device includes a stacked plurality of layers, each layer having a memory array, and each memory array having a string of memory cells. The programming method includes, for each unselected string associated with an unselected layer in the plurality of layers, charging the channel of memory cells associated with unselected string with a shut-off voltage, and thereafter programming a selected string associated with a selected layer in the plurality of layers. | 07-02-2009 |
20090168534 | THREE-DIMENSIONAL MEMORY DEVICE WITH MULTI-PLANE ARCHITECTURE - Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat formed on the first layer and a fourth mat formed on the second layer. The second and fourth mats share a bit line. Each one of the first through fourth mats includes a plurality of blocks and a block associated with the first plane is simultaneously accessed with a block of the second plane. | 07-02-2009 |
20090180323 | Nonvolatile memory device, program method thereof, and memory system including the same - A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program start voltage of normal memory cells and a program start voltage of the tail-bit memory cells independently based upon the tail-bit flag information. | 07-16-2009 |
20090185422 | Flash memory device having row decoders sharing single high voltage level shifter, system including the same, and associated methods - A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second. memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit. | 07-23-2009 |
20090213652 | PROGRAMMING METHOD FOR NON-VOLATILE MEMORY DEVICE - Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse. | 08-27-2009 |
20090213661 | NON-VOLATILE MEMORY DEVICE ADAPTED TO REDUCE COUPLING EFFECT BETWEEN STORAGE ELEMENTS AND RELATED METHODS - A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array. | 08-27-2009 |
20090219758 | MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY - A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2 | 09-03-2009 |
20090257297 | MULTI-CHIP SEMICONDUCTOR DEVICE PROVIDING ENHANCED REDUNDANCY CAPABILITIES - A semiconductor device including a plurality of semiconductor chips is provided. A semiconductor device includes a storing unit in which redundancy information portions are stored, and a comparing unit comparing a current address to the redundancy information portions and enabling or disabling operation of a semiconductor device based on the comparison result. | 10-15-2009 |
20090273977 | MULTILAYERED NONVOLATILE MEMORY WITH ADAPTIVE CONTROL - A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters. | 11-05-2009 |
20100027309 | SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS - A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips | 02-04-2010 |
20100027337 | Nonvolatile memory device extracting parameters and nonvolatile memory system including the same - The nonvolatile memory device includes a memory cell array having a plurality of memory blocks and a control logic circuit configured to store a parameter to access at least one of the plurality of memory blocks, configured to detect a variation of the parameter while accessing the at least one the memory block, and configured to store the varied parameter into the memory cell array in accordance with a result of the detection, wherein the control logic circuit is configured to utilize the varied parameter, which is stored in the memory cell array, while accessing the at least one memory block. | 02-04-2010 |
20100046290 | FLASH MEMORY DEVICE AND MEMORY SYSTEM - A flash memory device includes a first switch connecting one of a first cell string and a second cell string to a first bit line selectively, a second switch connecting the second cell string to a second bit line, and a control logic circuit providing bias voltages to the first and second cell strings through the first and second bit lines respectively and controlling the first and second cell stings to be simultaneously programmed. | 02-25-2010 |
20100065894 | Semiconductor Device Having a Field Effect Source/Drain Region - A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device. | 03-18-2010 |
20100067305 | NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD WITH IMPROVED PASS VOLTAGE WINDOW - A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a program voltage applied to the selected word line, and a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and control logic controlling the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and generation of the pass voltage, such that the program voltage is incrementally increased. | 03-18-2010 |
20100091571 | NONVOLATILE MEMORY DEVICE WITH NAND CELL STRINGS - A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage. | 04-15-2010 |
20100103737 | Read Compensation Circuits and Apparatus Using Same - A read compensation circuit is provided. The read compensation circuit corrects a read error occurring in an erased cell based on a pattern of programmed cells adjacent to the erased cell. The read compensation circuit also transmit program state information of a memory cell stored in a page buffer to another page buffer through a bit line, thereby allowing page buffers to easily detect and correct errors occurring in memory cells. | 04-29-2010 |
20100125701 | Multi-Level Non-Volatile Memory Device, Memory System Including the Same, and Method of Operating the Same - Methods of programming nonvolatile memory devices include programming a plurality of nonvolatile multi-state memory cells in the non-volatile memory device with state-converted data derived from non-state-converted data. This state-converted data may be associated with a greater number of erased states relative to the non-state-converted data, when programmed into the plurality of nonvolatile memory cells. The methods also include generating a flag having a value that indicates which ones of the plurality of nonvolatile memory cells have been programmed with data that is swapped with data in other ones of the plurality of nonvolatile memory cells. This flag may also be programmed into the nonvolatile memory device. Operations may also be performed to read the state-converted data (and flag) from the plurality of nonvolatile memory cells and then decode the state-converted data into the non-state-converted data, based on the value of the flag. | 05-20-2010 |
20100165731 | MEMORY DEVICE AND OPERATING METHOD - A method of operating a memory device includes; defining a plurality of read levels, using the plurality of read levels to determine electrical property differences between first and second memory cells adjacent dispose along a common word line, and determining read data stored in the first and second memory cells in relation to the determination of electrical property differences between the first and second memory cells. | 07-01-2010 |
20100195387 | NON-VOLATILE MEMORY DEVICE AND ISPP PROGRAMMING METHOD - A method programming a non-volatile memory device using an incremental step pulse programming (ISPP) scheme is disclosed. The method includes operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation and a verify operation are alternately repeated, and operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is constant, and during which the program operation and the verify operation are alternately repeated, wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition. | 08-05-2010 |
20100241929 | Semiconductor Memory Device for Performing Additional ECC Correction According to Cell Pattern and Electronic System Including the Same - A semiconductor memory device for performing additional error correction code (ECC) correction according to a cell pattern and an electronic system including the same are provided. The semiconductor memory device includes a memory cell array configured to store user data; and an ECC engine configured to perform first ECC encoding on the user data, output a result of the first ECC encoding as ECC information, detect a predetermined cell pattern based on the user data, and additionally perform second ECC encoding on data of a cell corresponding to the predetermined cell pattern detected. Accordingly, data errors that may occur due to a certain cell pattern are prevented. | 09-23-2010 |
20100246266 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block. | 09-30-2010 |
20110058427 | FLASH MEMORY DEVICE CONFIGURED TO REDUCE COMMON SOURCE LINE NOISE, METHODS OF OPERATING SAME, AND MEMORY SYSTEM INCORPORATING SAME - A flash memory device comprises memory cells connected between a bit line and a common source line, word lines connected to the memory cells, a common source line feedback circuit connected to a common source line (CSL) to detect the voltage level of the common source line, and a CSL feedback control logic configured to control a voltage level of a selected word line or a selected bit line to be compensated to a substantially constant value during a sensing operation of the memory cells based on the detected voltage level of the CSL. | 03-10-2011 |
20110110154 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises applying a gradually increasing program voltage to a memory cell, determining the number of verify voltages to be applied to the memory cell during a program loop based on the change of a threshold voltage from an initial state of the memory cell to a target state, and applying at least one of the determined verify voltages to the memory cell to verify whether the memory cell is programmed to the target state. | 05-12-2011 |
20110131367 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE, AND WEAR LEVELING METHOD FOR NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a memory core and a controller for controlling the wear level of a memory block in the nonvolatile memory device. The controller determines the wear level of a memory block by obtaining data of an actual wear level from a charge measurement cell of a selected region of the memory cell, and stores the wear level of the selected region in an erase count table. | 06-02-2011 |
20110161571 | FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING FLASH MEMORY DEVICE - A flash memory device performs a program operation using an incremental step pulse programming (ISPP) scheme comprising a plurality of program loops. In each of the program loops, a program pulse operation is performed to increase the threshold voltages of selected memory cells, and a program verify operation is performed to verify a program status of the selected memory cells. The program verify operation can be selectively skipped in some program loops based on a voltage increment of one or more of the program pulse operations, an amount by which threshold voltages of the selected memory cells are to be increased in the ISPP scheme, or a total number of program loops of the ISPP scheme. | 06-30-2011 |
20110164445 | SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS - A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips | 07-07-2011 |
20110194346 | FLASH MEMORY DEVICE USING ADAPTIVE PROGRAM VERIFICATION SCHEME AND RELATED METHOD OF OPERATION - A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state. | 08-11-2011 |
20110280066 | SEMICONDUCTOR DEVICE HAVING A FIELD EFFECT SOURCE/DRAIN REGION - A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device. | 11-17-2011 |
20110280070 | NONVOLATILE MEMORY DEVICE, SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE, AND READ OPERATION OF NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a memory cell array, a page buffer, and a control circuit. The memory cell array comprises multi-level cells configured to store hard decision data bits. The page buffer is configured to sense whether each of the multi-level cells assumes an on-cell state or an off-cell state in response to a first read voltage applied to a selected wordline during a first read operation, to set first soft decision data bits according to the first read operation, and to sense one or more hard decision data bits from each of the multi-level cells in response to a second read voltage applied to the selected wordline in a second read operation. The control circuit is configured to control the first read operation and the second read operation to be performed in succession. | 11-17-2011 |
20110296087 | METHOD OF MERGING BLOCKS IN A SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR MEMORY DEVICE TO PERFORM A METHOD OF MERGING BLOCKS - In a method of merging blocks in a semiconductor memory device according to example embodiments, a plurality of data are written into one or more first blocks using a first program method. One or more merge target blocks that are required to be merged are selected among the one or more first blocks. A merge-performing block for a block merge operation is selected among the one or more first blocks and one or more second blocks. A plurality of merge target data are written from the merge target blocks into the merge-performing block using a second program method that is different from the first program method. | 12-01-2011 |
20120039122 | MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY - A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2 | 02-16-2012 |
20120134207 | Non-Volatile Memory Device And Read Method Thereof - In one embodiment, the method for reading memory cells in an array of non-volatile memory cells includes reading data from a memory cell using a set of hard decision voltages and at least a first set of soft decision voltages based on a single read command. | 05-31-2012 |
20120134213 | METHOD COMPENSATION OPERATING VOLTAGE, FLASH MEMORY DEVICE, AND DATA STORAGE DEVICE - Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line. | 05-31-2012 |
20120140557 | PROGRAMMING METHOD FOR NON-VOLATILE MEMORY DEVICE - Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse. | 06-07-2012 |
20120203959 | NON-VOLATILE MEMORY, SYSTEM INCLUDING THE SAME, AND METHOD OF PROGRAMMING THE SAME - A method of programming a non-volatile memory that includes dumping first page data loaded to a cache latch to a first data latch and backing up the first page data to a second data latch. | 08-09-2012 |
20120262975 | SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS - A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips | 10-18-2012 |
20130010539 | NONVOLATILE MEMORY DEVICE PROVIDING NEGATIVE VOLTAGE - Disclosed is a nonvolatile memory device which includes memory blocks, a pre-decoder, and a row decoder. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals. | 01-10-2013 |
20130015588 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region. | 01-17-2013 |
20130021847 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block. | 01-24-2013 |
20130077374 | STACKED SEMICONDUCTOR APPARATUS, SYSTEM AND METHOD OF FABRICATION - A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits. | 03-28-2013 |
20130208541 | FLASH MEMORY DEVICE USING ADAPTIVE PROGRAM VERIFICATION SCHEME AND RELATED METHOD OF OPERATION - A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state. | 08-15-2013 |
20130208543 | NON-VOLATILE MEMORY DEVICE AND ISPP PROGRAMMING METHOD - A method programming a non-volatile memory device using an incremental step pulse programming (ISPP) scheme is disclosed. The method includes operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation and a verify operation are alternately repeated, and operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is constant, and during which the program operation and the verify operation are alternately repeated, wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition. | 08-15-2013 |
20130301352 | METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE METHOD - A method of programming a nonvolatile memory device including multi-level cells that store multi-bit data, includes performing a pre-programming operation that programs at least some of the multi-level cells to a plurality of intermediate states which are different from an erased state, and performing a main programming operation that programs the multi-level cells to a plurality of target states corresponding to the multi-bit data. At least some of the intermediate program states have threshold voltage distributions that partially overlap each other. | 11-14-2013 |
20140016410 | MEMORY DEVICE AND METHOD ADJUSTING READ VOLTAGE ACCORDING TO VARYING THRESHOLD VOLTAGE DISTRIBUTIONS - A memory device comprises a memory cell that is in one of an erase state and first through N-th program states (N>2). The memory device can be read by determining a first read voltage between the erase state and the first program state based on variations of respective threshold voltage distributions of the erase state and the first program state, and determining one among second through N-th read voltages based on variations in respective threshold voltage distributions of two adjacent program states among the first through N-th program states, and determining remaining read voltages among the second through N-th read voltages based on the one read voltage. | 01-16-2014 |
20140022853 | MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF CONTROLLING READ VOLTAGE OF THE MEMORY DEVICE - A memory device includes a memory cell array and a page buffer unit. The memory cell array includes multiple memory cells. The page buffer unit performs a logic operation on data sequentially read from the memory cells at different voltage levels, based on the read data and a read direction of applying the different voltage levels. | 01-23-2014 |
20140029355 | MEMORY DEVICE AND METHOD OF DETERMINING READ VOLTAGE OF MEMORY DEVICE - A method of operating a memory device comprises applying an initial read voltage to a selected wordline to perform a read operation on memory cells connected to the selected wordline, determining whether a read failure occurs with respect to one or more of the memory cells, upon determining that a read failure has occurred with respect to some of the memory cells, determining threshold voltage distribution information for distinct groups of the memory cells, and determining a new read voltage to be applied to the selected wordline based on the threshold voltage distribution information. | 01-30-2014 |
20140043904 | MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A memory system performs a first sensing operation to sense whether multi-level cells assume an on-cell state or an off-cell state in response to a first read voltage applied to a selected word line. It then supplies a pre-charge voltage to bit lines corresponding to multi-level cells that have been sensed as assuming the off-cell state in response to the first read voltage, and it performs a second sensing operation with the supplied pre-charge voltage to sense whether each of the multi-level cells that have been sensed as assuming the off-cell state assumes an on-cell state or an off-cell state in response to a second read voltage applied to the selected word line. | 02-13-2014 |
20140063945 | READ METHOD FOR NONVOLATILE MEMORY DEVICE, AND DATA STORAGE SYSTEM USING THE SAME - Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step. | 03-06-2014 |
20140104917 | SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS - A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips | 04-17-2014 |
20140104955 | PROGRAMMING NONVOLATILE MEMORY DEVICE USING PROGRAM VOLTAGE WITH VARIABLE OFFSET - A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias. | 04-17-2014 |
20140129902 | APPARATUS AND METHOD OF OPERATING MEMORY DEVICE - A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array. | 05-08-2014 |
20140129903 | METHOD OF OPERATING MEMORY DEVICE - A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage. | 05-08-2014 |
20140167289 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region. | 06-19-2014 |
20140169101 | METHOD COMPENSATION OPERATING VOLTAGE, FLASH MEMORY DEVICE, AND DATA STORAGE DEVICE - Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line. | 06-19-2014 |
20140185378 | MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY - A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2″ pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits. | 07-03-2014 |
20150029796 | MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF CONTROLLING READ VOLTAGE OF THE MEMORY DEVICE - A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation | 01-29-2015 |