Patent application number | Description | Published |
20110122094 | OPTICAL TOUCH APPARATUS AND OPTICAL TOUCH DISPLAY APPARATUS - An optical touch apparatus includes a light source, light guide unit, and optical detector. The light source next to the display area emits a beam. The light guide unit next to the display area and in the transmission path of the beam includes a light guide body and a Lambertian scattering structure. The light guide body has first, second, third, fourth, and light incident surfaces. The beam enters the light guide body through the light incident surface and is transmitted from the first surface to a sensing space in front of the display area. The Lambertian scattering structure is disposed on at least one of the second, third, and fourth surfaces for scattering the beam to the first surface. The optical detector next to the display area senses a change in light intensity of the beam in the sensing space. An optical touch display apparatus is also provided. | 05-26-2011 |
20110122097 | OPTICAL TOUCH APPARATUS - An optical touch apparatus includes a light source capable of emitting a beam, a light guide unit disposed in a transmission path of the beam, and an optical detector. The light guide unit includes a light guide body having a first surface, a second surface, a third surface, a fourth surface, and a scattering structure disposed on at least one of the second surface, the third surface, and the fourth surface. The beam is capable of entering the light guide body, being scattered to the first surface by the scattering structure, and then being transmitted to a sensing space. The scattering structure includes separated scattering patterns including a resin composition and scattering particles dispersed in the resin composition. The ratio of the weight percentage of the scattering particles to the weight percentage of the resin composition is equal to or greater than 0.1. | 05-26-2011 |
Patent application number | Description | Published |
20100271323 | Soft Digital Tablet - A soft digital tablet is disclosed. The soft digital tablet comprises a soft case, an antenna board and a control circuit board. The antenna board and the control circuit board induct and process electromagnetic signal from a digital pen, and transmit the processed electromagnetic signal to a host via a transmission line. | 10-28-2010 |
20110000720 | Flexible Tablet - A flexible tablet is disclosed, and particular disclosed a flexible tablet having both of a hard housing structure and a soft housing structure. The flexible tablet fix a control board in the hard housing structure for preventing the control board form bending and break resulting from external force. In the flexible tablet, the soft housing structure is applied instead of the hard housing of a conventional tablet to fix a sensing board therein. Therefore, the soft housing structure and the sensing board are integrated to form a flexible writing member of the flexible tablet. As a consequence of foregoing structure, the tablet is flexible and convenient to be stored and carried, and the cost of the tablet is reduced. | 01-06-2011 |
20110175854 | ELECTROMAGNETIC POINTER - An electromagnetic pointer is disclosed. The electromagnetic pointer comprises a pen holder assembly, a circuit board, a metal rod, a ferrite core with coils and a trigger device. The diameter of the pen holder assembly is less than 6 mm. The circuit board comprises a resonance circuit. The metal rod has a low permeability. The ferrite core with coil constitutes an inductor and the coil electrically connects to the circuit board through a conductive wire to complete the resonance circuit. The ferrite core has a hollow center so that the metal rod can move through to trigger the trigger device and change electric properties of the resonance circuit. | 07-21-2011 |
Patent application number | Description | Published |
20080237831 | MULTI-CHIP SEMICONDUCTOR PACKAGE STRUCTURE - A multi-chip semiconductor package structure is disclosed according to the present invention, the package structure includes: a carrier board having a first surface, a second surface, and at least an opening penetrating the first and second surfaces, the first and second surfaces each having electrically connecting pads; a semiconductor component received in the opening, the semiconductor component has a first active surface and a second active surface, and each of the first and second active surfaces has a plurality of electrode pads; a plurality of first conductive elements electrically connected to the electrically connecting pads of the first and second surfaces of the carrier board with the electrode pads of the first and second active surfaces of the semiconductor component; and a molding material formed on a portion of the first surface of the carrier board, the first active surface of the semiconductor component, a portion of the second surface of the carrier board, and the second active surface of the semiconductor component, and adapted to cover the first conductive elements; thereby forming a module structure for electrical connection with other modules or stacked devices, and further enhancing electrical functions. | 10-02-2008 |
20080237832 | MULTI-CHIP SEMICONDUCTOR PACKAGE STRUCTURE - A multi-chip semiconductor package structure is disclosed, including a carrier board having a first and an opposing second surfaces and formed with at least an opening penetrating the first and second surfaces, wherein a plurality of electrically connecting pads are formed on the first and second surfaces of the carrier board, respectively; a semiconductor component disposed in the opening, the semiconductor component having a first and a second active surfaces each with a plurality of electrode pads being formed thereon; a third semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for electrically connecting with the electrically connecting pads on the first surface of the carrier board and the electrode pads on the first active surface of the semiconductor component; and a fourth semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for electrically connecting with the electrically connecting pads on the second surface of the carrier board and the electrode pads on the second active surface of the semiconductor component, thereby providing a modularized structure for electrically connecting with other modules or stack devices and enhancing electrical functionality. | 10-02-2008 |
20080237833 | MULTI-CHIP SEMICONDUCTOR PACKAGE STRUCTURE - A multi-chip semiconductor package structure is disclosed according to the present invention. The package structure includes: a carrier board having a first surface, a second surface, and at least one opening penetrating the first and second surfaces, the first and second surfaces each being formed with a plurality of electrically connecting pads thereon; a semiconductor component received in the opening and having first and second active surfaces, the first and second active surfaces each being formed with a plurality of electrode pads thereon; a plurality of first conductive elements electrically connected to the electrically connecting pads on the second surface of the carrier board and the electrode pads on the second active surface of the semiconductor component; a semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads electrically connected to the electrically connecting pads on the first surface of the carrier board and the electrode pads on the first active surface of the semiconductor component; and a molding material formed on a portion of the second surface of the carrier board and the second active surface of the semiconductor component to cover the first conductive elements. The present invention provides a modularized structure capable of electrically connecting to other modules or stacked devices as well as enhancing electrical performance. | 10-02-2008 |
20090091903 | Stack structure of circuit boards embedded with semiconductor chips - A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards. | 04-09-2009 |
20090200658 | CIRCUIT BOARD STRUCTURE EMBEDDED WITH SEMICONDUCTOR CHIPS - A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured. | 08-13-2009 |
Patent application number | Description | Published |
20080303102 | Strained Isolation Regions - An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure. | 12-11-2008 |
20130099350 | Semiconductor Device and Method of Manufacture - A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material. | 04-25-2013 |
20130137251 | Uniform Shallow Trench Isolation Regions and the Method of Forming the Same - A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively. | 05-30-2013 |
20130277760 | Dummy FinFET Structure and Method of Making Same - A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET. | 10-24-2013 |
20140127879 | Semiconductor Device and Method of Manufacture - A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgas sing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material. | 05-08-2014 |
20140231919 | Fin Deformation Modulation - A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively. | 08-21-2014 |
20140242776 | Strained Isolation Regions - A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure. | 08-28-2014 |
20140252497 | Isolation Region Gap Fill Method - An isolation region gap fill method comprises depositing a first dielectric material over a semiconductor device through a flowable deposition process or other gap fill deposition processes, wherein the semiconductor device includes a first FinFET comprising a plurality of first fins and a second FinFET comprising a plurality of second fins. The method further comprises removing the first dielectric material between the first FinFET and the second FinFET to form an inter-device gap, depositing a second dielectric material into the inter-device gap and applying an annealing process to the semiconductor device. | 09-11-2014 |
20140264491 | Semiconductor Strips with Undercuts and Methods for Forming the Same - An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip. | 09-18-2014 |
20150014790 | Fin Deformation Modulation - A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively. | 01-15-2015 |
Patent application number | Description | Published |
20090002614 | Liquid crystal display panel - A liquid crystal display (LCD) panel includes a first substrate, a first electrode, a second substrate, and a liquid crystal layer. The first electrode is disposed on the first substrate. The first electrode has a main slit, a first sub-slit and a first pinhole. The first sub-slit is connected to the main slit and the first pinhole is separated from the main slit. The second substrate is disposed over the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. | 01-01-2009 |
20090040172 | Liquid crystal display and the backlight indicating apparatus and method thereof - A liquid crystal display has a backlight module and an indicator. The indicator is used to detect the light brightness of the backlight module, and announces a warning when the light brightness is lower than a predetermined value. The indicator has at least one color light detection unit that includes a detector, an analog-to-digital converter (ADC), a controller and a warning display. The detector detects the brightness of a color light from the backlight module to generate a light brightness voltage. The ADC converts the light brightness voltage into a digital signal. The controller determines whether the brightness of the color light is lower than the predetermined value or not according to the digital signal. When the brightness of the color light is lower than the predetermined value, the controller makes the warning display announce the warning. | 02-12-2009 |
20100188615 | Display Device, Manufacturing Method Thereof, and Color Adjusting Method Used Thereon - A display device, a manufacturing method thereof, and a color adjusting method used thereon are provided. The display device includes a blue light source and a display panel which includes a substrate having a color adjusting layer, a blue filter layer, and an inner polarizer disposed thereon. The color adjusting layer includes a plurality of color excitation units, wherein each color excitation unit contains a plurality of wavelength transformation materials. The blue filter layer allows only blue light to pass therethrough and absorbs other color light. The blue light passes through the inner polarizer and the blue filter layer to reach the color excitation units. The blue light further excites the wavelength transformation materials to generate different color light. A part of the different color light is transmitted to and absorbed by the blue filter layer. | 07-29-2010 |
20110080396 | DRIVING METHOD FOR REDUCING IMAGE STICKING - A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect. | 04-07-2011 |
20110115780 | DRIVING METHOD FOR REDUCING IMAGE STICKING - A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect. | 05-19-2011 |
20110228187 | LIQUID CRYSTAL DISPLAY PANEL AND RELATED DEVICE - A liquid crystal display panel includes a first substrate, a second substrate, a first electrode, a second electrode, a third electrode, an isolating layer, and a conductor. The first electrode is disposed between the first substrate and the isolating layer, on which the conductor is disposed. Each of the second and third electrodes is disposed on the second substrate and includes a contact surface. The second and third electrodes are not in contact with each other and are separated by a gap. The conductor is disposed in accordance with the location of the gap. | 09-22-2011 |
20110228205 | LIQUID CRYSTAL DISPLAY PANEL AND RELATED DEVICE - A liquid crystal display panel includes a first substrate, a second substrate, a first electrode, a second electrode, a third electrode, an isolating layer, and a conductor. The first electrode is disposed between the first substrate and the isolating layer, on which the conductor is disposed. Each of the second and third electrodes is disposed on the second substrate and includes a contact surface. The second and third electrodes are not in contact with each other and are separated by a gap. The conductor is disposed in accordance with the location of the gap. | 09-22-2011 |
20110285693 | DRIVING METHOD FOR REDUCING IMAGE STICKING - A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect. | 11-24-2011 |
20120105780 | LIQUID CRYSTAL DISPLAY INTEGRATED WITH SOLAR CELL MODULE - The present invention provides a liquid crystal display integrated with a solar cell module, which includes a first transparent substrate, a second transparent substrate, a cholesteric liquid crystal layer, a third transparent substrate, and a photoelectric conversion layer. The second transparent substrate is disposed on a side of the first transparent substrate, and the cholesteric liquid crystal layer is disposed between the first transparent substrate and the second transparent substrate. The third transparent substrate is disposed on the other side of the first transparent substrate opposite to the second transparent substrate, and the photoelectric conversion layer is adhered between the first transparent substrate and the third transparent substrate. The first transparent substrate, the photoelectric conversion layer and the third transparent substrate constitute the solar cell module. | 05-03-2012 |
20120200551 | DRIVING METHOD FOR REDUCING IMAGE STICKING - A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect. | 08-09-2012 |
20130057513 | LIQUID CRYSTAL DISPLAY PANEL AND RELATED DEVICE - A liquid crystal display panel includes a first substrate, a second substrate, a first electrode, a second electrode, a third electrode, an isolating layer, and a conductor. The first electrode is disposed between the first substrate and the isolating layer, on which the conductor is disposed. Each of the second and third electrodes is disposed on the second substrate and includes a contact surface. The second and third electrodes are not in contact with each other and are separated by a gap. The conductor is disposed in accordance with the location of the gap. | 03-07-2013 |