Myoung-Kyu
Myoung Kyu Choi, Chungbuk KR
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20090170253 | Method of manufacturing semiconductor device - The present invention relates to a method of manufacturing a semiconductor device, in which a gate electrode is formed in a T-shape in order to increase the size of a top surface of the gate electrode, thereby providing a stable silicide forming condition and preventing contact misalignment. | 07-02-2009 |
Myoung Kyu Kim, Suwon-Si KR
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20080277278 | BIOSENSOR FOR DISEASE DIAGNOSIS - The present invention relates to a biosensor including: a bottom plate having a base film having a lead mounted at one side of the top surface thereof, an electrode member formed on the base film, a spacer formed on the top surface of the electrode member so as to secure a recess having a predetermined width formed on the electrode member, and an enzyme reaction layer formed transversely on the top surface of the electrode member in such a fashion as to be positioned in the recess of the spacer; and a top plate formed integrally with the bottom plate and having the same configuration as the bottom plate. | 11-13-2008 |
Myoung Kyu Seo, Gyeonggi-Do KR
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20140040538 | METHOD OF WRITING DATA, MEMORY, AND SYSTEM FOR WRITING DATA IN MEMORY - A method of writing data in a memory comprising a NAND cell array is disclosed, wherein a data output device completes the writing process only by transmitting the data and a start address for writing the data to the memory. | 02-06-2014 |
20140223080 | NON-VOLATILE MEMORY DEVICE, ELECTRONIC CONTROL SYSTEM, AND METHOD OF OPERATING THE NON-VOLATILE MEMORY DEVICE - Provided are a non-volatile memory device, an electronic control system, and a method of operating the non-volatile memory device. A non-volatile memory device according to an embodiment of the present invention includes a first NAND cell array including a first group of pages, and a second NAND cell array including a second group of pages. A plurality of X-decoders are at least one-to-one connected to the first and second NAND cell arrays. A control logic controls the plurality of X-decoders to simultaneously sense data of a first page corresponding to a start address from among the first group of pages, and data of a second page subsequent to the first page from among the second group of pages. | 08-07-2014 |
Myoung-Kyu Lee, Suwon-Si KR
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20080224958 | PLASMA DISPLAY DEVICE AND DRIVING APPARATUS THEREOF - In a plasma display device and a driving apparatus thereof, a scan electrode driver for applying a driving voltage to a scan electrode has a diode including a cathode coupled to a sustain voltage supplying power and an anode coupled to a switch for applying a reset rising waveform to the scan electrode. In the scan electrode driver, when a switch for applying a reset rising waveform is turned on, the voltage at the scan electrode is gradually increased by a voltage that is less than the sustain voltage due to the breakdown voltage of the diode. Therefore, the number of power sources is reduced simplifying the circuit configuration and reducing the plasma display device production cost. | 09-18-2008 |
20090002278 | Plasma display and driving method thereof - A plasma display device, which gradually increases the current to the panel capacitors is disclosed. The display uses an inductor to reduce the current spike which would otherwise occur and create large electromagnetic interference. | 01-01-2009 |
20090128526 | Plasma display device and driving apparatus thereof - A driver circuit for a plasma display panel is disclosed. The driver circuit has a switch which is shared between the reset driver portion of the driver circuit and the sustain driver portion of the driver circuit. The driver circuit sharing the switch between the two portions is smaller and cheaper than other driver circuits. | 05-21-2009 |
Myoung-Kyu Lee, Hwaseong-Si KR
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20140347802 | PORTABLE COMPUTING APPARATUS - A portable computing apparatus according to an exemplary embodiment of the present general inventive concept includes a first device, and a second device having a coupling groove where the first device is detechably coupled, where the first device has a first coupling position where a first end of the first device is coupled with the coupling groove by a first connection angle, and a second coupling position where a second end of the first device is coupled with a second connection angle different from the first connection angle. | 11-27-2014 |
Myoung-Kyu Park, Gyeonggi-Do KR
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20090290417 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device including a plurality of word lines; a plurality of bit lines intersecting the word lines; a plurality of memory cells corresponding to intersections of the word lines and the bit lines; a common control gate line commonly connected to the memory cells; and a common erasing gate line commonly connected to the memory cells. | 11-26-2009 |
Myoung-Kyu Park, Yongin-Si KR
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20090020844 | Semiconductor device having electrostatic discharge protection circuit and method of manufacturing the same - Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate. | 01-22-2009 |
20100123245 | Semiconductor integrated circuit devices and display apparatus including the same - A semiconductor integrated circuit device includes: an electrostatic discharge (ESD) impurity region formed in a substrate; a bump formed on the substrate; and a first wiring layer and a second wiring layer formed at the same level under the bump. The first and second wiring layers are separated from each other, and at least part of each of the first and second wiring layers are overlapped by the bump. The first wiring layer is electrically connected to the ESD impurity region and the bump, and the second wiring layer is insulated from the bump. | 05-20-2010 |
20110303961 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - A nonvolatile memory device including a cell array area in which a plurality of unit cells are arranged at least in one direction includes a plurality of memory transistors formed in the respective unit cells. Each memory transistor includes a gate pattern in which a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate are laminated, and first and second junction areas arranged on opposite sides of the gate pattern, wherein the gate patterns are separated in the one direction by unit cells. The to nonvolatile memory device also includes a first conduction interconnection which extends in the one direction and is arranged in a position that overlaps the control gate and a plurality of first contacts, at least one of which is arranged for each of the control gates to connect the control gates and the first conduction interconnection. | 12-15-2011 |
20110305084 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes; a first well having a first impurity concentration formed in a first region of a semiconductor substrate, a second well having a second impurity concentration different from the first impurity concentration formed in a second region of the semiconductor substrate, an access transistor with floating gate formed on the first region, and a control Metal Oxide Semiconductor (MOS) capacitor with one electrode formed on the second region. The floating gate and the one electrode are formed from respective portions of a unitary gate line extending across the first and second regions | 12-15-2011 |
20120003805 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode. | 01-05-2012 |