Taufique
Mohammed Taufique, Austin, TX US
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20100149849 | MEMORY ARRAY ON MORE THAN ONE DIE - For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed. | 06-17-2010 |
Mohammed H. Taufique, Austin, TX US
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20090001601 | MEMORY ARRAY ON MORE THAN ONE DIE - For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed. | 01-01-2009 |
Mohammed Hasan Taufique, Austin, TX US
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20140334049 | VOLTAGE DETECTOR WITH HIGH VOLTAGE PROTECTION - Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector. | 11-13-2014 |
Mohammed Hassan Taufique, Austin, TX US
Patent application number | Description | Published |
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20090059690 | Methods and apparatuses for operating memory - In one embodiment a low voltage high performance memory system is disclosed. The system can include a bit cell, a first pass gate coupled to the bit cell to receive a write signal, a second pass gate coupled to the bit cell to receive the write signal, and an supply current controller to reduce current to at least a portion of the bit cell and to supply current to another portion of the cell in response to a write control signal and a data signal during a bit cell transition. Reducing the current to a portion of the bit cell and supplying current to another portion of the bit cell during transition can allow the bit cell to transition to a different state faster and can reduce the effects of device variations that manifest during low voltage operation. Other embodiments are also disclosed. | 03-05-2009 |