Patent application number | Description | Published |
20080232440 | CHIP BLANKING AND PROCESSING IN SCDMA TO MITIGATE IMPULSE AND BURST NOISE AND/OR DISTORTION - A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication. | 09-25-2008 |
20090285343 | SYSTEM AND METHOD FOR CANCELING INTERFERENCE IN A COMMUNICATION SYSTEM - A filter settings generation operation includes sampling a communication channel to produce a sampled signal. The sampled signal is spectrally characterized across a frequency band of interest to produce a spectral characterization of the sampled signal. This spectral characterization may not include a signal of interest. The spectral characterization is then modified to produce a modified spectral characterization. Filter settings are then generated based upon the modified spectral characterization. Finally, the communication channel is filtered using the filter settings when the signal of interest is present on the communication channel. In modifying the spectral characterization, pluralities of spectral characteristics of the spectral characterization are independently modified to produce the modified spectral characterization. Modifications to the spectral characterization may be performed in the frequency domain and/or the time domain. One particular spectral modification that is performed is raising of the noise floor of the spectral characterization to meet a budgeted signal-to-noise ratio. Other spectral modifications include modifying spectral components corresponding to an expected interfering signal. In modifying these spectral characterizations, spectral components corresponding to a plurality of expected interfering signals may be modified. | 11-19-2009 |
20100180165 | SYSTEM AND METHOD OF UNCORRELATED CODE HOPPING IN A COMMUNICATIONS SYSTEM - A system and method are used to provide uncorrelated code hopping in a communications system. A shift register receives data. The shift register is clocked to shift the data. A scaler performs a scaling operation on the data with a numerical value of active codes. A truncator truncates the scaled data to its seven most significant bits to produce a pseudo random hop number. A code matrix shifter circularly shifts the active codes in a code matrix based on the pseudo random hop number to produce a circularly shifted code. A transmitter transmits the circularly shifted code. | 07-15-2010 |
20100229075 | CHIP BLANKING AND PROCESSING IN SCDMA TO MITIGATE IMPULSE AND BURST NOISE AND/OR DISTORTION - A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication. | 09-09-2010 |
20110135044 | System and Method for Canceling Interference in a Communication System - A filter settings generation operation includes sampling a communication channel to produce a sampled signal. The sampled signal is spectrally characterized across a frequency band of interest to produce a spectral characterization of the sampled signal. This spectral characterization may not include a signal of interest. The spectral characterization is then modified to produce a modified spectral characterization. Filter settings are then generated based upon the modified spectral characterization. Finally, the communication channel is filtered using the filter settings when the signal of interest is present on the communication channel. In modifying the spectral characterization, pluralities of spectral characteristics of the spectral characterization are independently modified to produce the modified spectral characterization. Modifications to the spectral characterization may be performed in the frequency domain and/or the time domain. One particular spectral modification that is performed is raising of the noise floor of the spectral characterization to meet a budgeted signal-to-noise ratio. Other spectral modifications include modifying spectral components corresponding to an expected interfering signal. In modifying these spectral characterizations, spectral components corresponding to a plurality of expected interfering signals may be modified. | 06-09-2011 |
20120230374 | Chip blanking and processing in SCDMA to mitigate impulse and burst noise and/or distortion - A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication. | 09-13-2012 |
20120243527 | Upstream burst noise measurement and characterization - Upstream burst noise measurement and characterization. One or more communication devices is implemented to detect and measure burst noise event(s) within channel(s) associated with communication link(s) within communication system(s) or network(s). Detection and measurement of a burst noise event may be made during active communications on one or more other channels, and may be made during active communications on two channels respectively adjacent to the channel on which the burst noise event is being detected and measured. The channel on which the burst noise event is detected and measured may be an unused channel. The detection and measurement of the burst noise event may be made during a quiet time slot within one of the channels. Correlation (e.g., with respect time) may be determined with respect to different respective layers within a communication device (e.g., with respect to MAC and PHY layers). | 09-27-2012 |
20120243597 | Upstream frequency response measurement and characterization - Upstream frequency response measurement and characterization. Signaling is provided between respective communication devices within a communication system. Based upon at least one of these signals, one of the communication devices captures a number of sample sets corresponding thereto at different respective frequencies (e.g., a different respective center frequencies, frequency bands, etc.). Then, spectral analysis is performed with respect to each of the sample sets to generate a respective and corresponding channel response estimate there from. After this number of channel response estimates is determined, they are combined or splice together to generate a full channel response estimate. In implementations including an equalizer, different respective sample sets may correspond to those that have undergone equalization processing and those that have not. | 09-27-2012 |
20120243648 | Characterization and assessment of communication channel average group delay variation - Characterization and assessment of communication channel average group delay variation. A signal having repeated signal components therein is received by a communication device, and that signal undergoes appropriate processing to determine respective amplitude and phase of a number of frequency bins. The phase difference from bin to bin (including respecting unwrapping, and proper normalization) is used to determine the group delay of a communication channel, or portion thereof, as a function of frequency. Multiple respective group delay measurements may be averaged to generate a wideband group delay of the communication channel as a function of frequency. Overlap between different respective band-edge portions of the communication channel may assist in generating a seamless continuous wideband spectrum estimation for use in determining the wideband group delay of the communication channel. | 09-27-2012 |
20130294377 | Robust Techniques for Upstream Communication Between Subscriber Stations and a Base Station - A number of features for enhancing the performance of a communication system, in which data is transmitted between a base station and a plurality of subscriber stations located different distances from the base station, are presented. The power transmission level, slot timing, and equalization of the subscriber stations are set by a ranging process. Data is transmitted by the subscriber stations in fragmented form. Various measures are taken to make transmission from the subscriber stations robust. The uplink data transmission is controlled to permit multiple access from the subscriber stations. | 11-07-2013 |
20140079102 | Physical Layer (PHY) Link Signaling for Cable Networks - Embodiments include systems and methods for enabling a physical layer (PHY) link signaling channel between a network termination modem and a cable modem in a cable network. The PHY link signaling channel is embedded within the same multi-carrier channel as the data and enables PHY link up between the network termination modem and cable modem without involvement of higher layers (e.g., MAC). The PHY link signaling channel can be implemented in the downstream (from the network termination modem to the cable modem(s)) or in the upstream from a cable modem to the network termination modem. Embodiments are applicable to any known cable network, and particularly to cable networks implementing the DOCSiS and EPoC standards. | 03-20-2014 |
20150358437 | Physical Layer (PHY) Link Signaling for Cable Networks - Embodiments include systems and methods for enabling a physical layer (PHY) link signaling channel between a network termination modem and a cable modem in a cable network. The PHY link signaling channel is embedded within the same multi-carrier channel as the data and enables PHY link up between the network termination modem and cable modern without involvement of higher layers (e.g., MAC). The PHY link signaling channel can be implemented in the downstream (from the network termination modem to the cable modem(s)) or in the upstream from a cable modem to the network termination modem. Embodiments are applicable to any known cable network, and particularly to cable networks implementing the DOCSIS and EPoC standards. | 12-10-2015 |
Patent application number | Description | Published |
20090296794 | System and Method for Performing Ranging in a Cable Modem System - The present invention provides a system and method for performing ranging operations in a cable modem system. In accordance with embodiments of the present invention, transmission times, transmission power levels, transmission carrier frequencies, and pre-equalization parameters are adjusted to provide for robust operation of the cable modem system. More particularly, iterative processing steps are used to provide coefficient ordering, scaling, and aligning between the multiple cable modems and the cable modem termination system present in a cable modem system. | 12-03-2009 |
20110013534 | Receiver Having Integrated Spectral Analysis Capability - A method of managing traffic in a communications channel includes the steps of receiving a subscriber ID corresponding to a subscriber, performing a spectral analysis on a signal received from the subscriber within a time interval identified by the subscriber ID, and adjusting transmission characteristics of the subscriber based on the spectral analysis. | 01-20-2011 |
20110026423 | Robust Techniques for Upstream Communication Between Subscriber Stations and a Base Station - A number of features for enhancing the performance of a communication system, in which data is transmitted between a base station and a plurality of subscriber stations located different distances from the base station, are presented. The power transmission level, slot timing, and equalization of the subscriber stations are set by a ranging process. Data is transmitted by the subscriber stations in fragmented form. Various measures are taken to make transmission from the subscriber stations robust. The uplink data transmission is controlled to permit multiple access from the subscriber stations. | 02-03-2011 |
20140286183 | Receiver Having Integrated Spectral Analysis Capability - A method of managing traffic in a communications channel includes the steps of receiving a subscriber ID corresponding to a subscriber, performing a spectral analysis on a signal received from the subscriber within a time interval identified by the subscriber ID, and adjusting transmission characteristics of the subscriber based on the spectral analysis. | 09-25-2014 |
Patent application number | Description | Published |
20140153673 | Adaptive decoding based on signal to noise ratio (SNR) - A communication device is configured adaptively to process a receive signal based on noise that may have adversely affected the signal during transition via communication channel. The device may be configured to identify those portions of the signal of the signal that are noise-affected (e.g., noise-affected sub-carriers of an orthogonal frequency division multiplexing (OFDM) signal), or the device may receive information that identifies those portions of the signal that are noise-affected from one or more other devices. The device may be configured to perform the modulation processing of the received signal to generate log-likelihood ratios (LLRs) for use in decoding the signal. Those LLRs associated with noise-affected portions of the signal are handled differently than LLRs associated with portions of the signal that are not noise-affected. The LLRs may be scaled based on signal to noise ratio(s) (SNR(s)) associated with the signal (e.g., based on background noise, burst noise, etc.). | 06-05-2014 |
20140177741 | OFDM or OFDMA signaling for ranging and data - A communication device is operative to generate and orthogonal frequency division multiplexing (OFDM) symbol that includes one or more data and ranging modulation symbols. The data and ranging modulation symbols may be included within different sub-carriers of the OFDM symbol. The OFDM symbol is used to generate an OFDM symbol pair in the frequency domain (FDOM). After conversion from the FDOM to the time domain (TDOM), the OFDM symbol pair may then undergoes post-processing in the TDOM before transmission. Such post-processing may include the addition of cyclic prefix (CP) and cyclic suffix (CS) to the OFDM symbol pair in the TDOM as well as filtering using a window function. The OFDM symbol may be generated as an orthogonal frequency division multiple access (OFDMA) symbol, and two were more OFDM symbols or OFDMA symbols may be arranged in a frame. | 06-26-2014 |
20140201588 | Low density parity check (LDPC) coding in communication systems - A communication device is configured to encode and/or decode low density parity check (LDPC) coded signals. Such LDPC coded signals are characterized by LDPC matrices having a particular form. An LDPC matrix may be partitioned into a left hand side matrix and the right hand side matrix. The right hand side matrix can be lower triangular such that all of the sub-matrices therein are all-zero-valued sub-matrices (e.g., all of the elements within an all-zero-valued sub-matrix have the value of “0”) except for those sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to the left of the main diagonal. A device may be configured to employ different LDPC codes having different LDPC matrices for different LDPC coded signals. The different LDPC matrices may be based generally on a common form (e.g., with a right hand side matrix as described above). | 07-17-2014 |
20150139290 | Upstream frequency response measurement and characterization - Upstream frequency response measurement and characterization. Signaling is provided between respective communication devices within a communication system. Based upon at least one of these signals, one of the communication devices captures a number of sample sets corresponding thereto at different respective frequencies (e.g., a different respective center frequencies, frequency bands, etc.). Then, spectral analysis is performed with respect to each of the sample sets to generate a respective and corresponding channel response estimate there from. After this number of channel response estimates is determined, they are combined or splice together to generate a full channel response estimate. In implementations including an equalizer, different respective sample sets may correspond to those that have undergone equalization processing and those that have not. | 05-21-2015 |
20150326418 | OFDM or OFDMA signaling for ranging and data - A communication device is operative to generate and orthogonal frequency division multiplexing (OFDM) symbol that includes one or more data and ranging modulation symbols. The data and ranging modulation symbols may be included within different sub-carriers of the OFDM symbol. The OFDM symbol is used to generate an OFDM symbol pair in the frequency domain (FDOM). After conversion from the FDOM to the time domain (TDOM), the OFDM symbol pair may then undergoes post-processing in the TDOM before transmission. Such post-processing may include the addition of cyclic prefix (CP) and cyclic suffix (CS) to the OFDM symbol pair in the TDOM as well as filtering using a window function. The OFDM symbol may be generated as an orthogonal frequency division multiple access (OFDMA) symbol, and two were more OFDM symbols or OFDMA symbols may be arranged in a frame. | 11-12-2015 |
Patent application number | Description | Published |
20090001443 | NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC - Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed. | 01-01-2009 |
20090057744 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 03-05-2009 |
20090242961 | RECESSED CHANNEL SELECT GATE FOR A MEMORY DEVICE - A memory device comprising one or more recessed channel select gates and at least one charge trapping layer. | 10-01-2009 |
20090283817 | FLOATING GATE STRUCTURES - Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon. | 11-19-2009 |
20090321809 | GRADED OXY-NITRIDE TUNNEL BARRIER - Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed. | 12-31-2009 |
20100197131 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 08-05-2010 |
20120032252 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 02-09-2012 |
20140159136 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 06-12-2014 |
Patent application number | Description | Published |
20090111265 | SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 04-30-2009 |
20090140325 | FORMING METAL-SEMICONDUCTOR FILMS HAVING DIFFERENT THICKNESSES WITHIN DIFFERENT REGIONS OF AN ELECTRONIC DEVICE - A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness. | 06-04-2009 |
20100099249 | SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 04-22-2010 |
20110175158 | DUAL CHARGE STORAGE NODE MEMORY DEVICE AND METHODS FOR FABRICATING SUCH DEVICE - A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers. | 07-21-2011 |
20130277733 | FLASH MEMORY DEVICES AND METHODS FOR FABRICATING SAME - Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material. | 10-24-2013 |
Patent application number | Description | Published |
20080237683 | HIGH-K TRILAYER DIELECTRIC DEVICE AND METHODS - Methods and structures are described for reducing a gate leakage current and increasing gate coupling ratio in a semiconductor device. In some embodiments, nitride layers are used to limit the oxidation of adjacent silicon gate regions due to oxygen in an intermediate insulator. In various embodiments, the intermediate insulator includes a high-κ dielectric material. Apparatus according to embodiments of the invention are also disclosed. | 10-02-2008 |
20080237691 | SELF-ALIGNED CHARGE-TRAPPING LAYERS FOR NON-VOLATILE DATA STORAGE, PROCESSES OF FORMING SAME, AND DEVICES CONTAINING SAME - A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device. | 10-02-2008 |
20090097320 | Memory Cells, Electronic Systems, Methods Of Forming Memory Cells, And Methods of Programming Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones. | 04-16-2009 |
20090146126 | PROBE-BASED MEMORY - Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory. | 06-11-2009 |
20090273016 | NANOCRYSTAL FORMATION USING ATOMIC LAYER DEPOSITION AND RESULTING APPARATUS - Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures. | 11-05-2009 |
20100176432 | Memory Cells, Methods Of Forming Dielectric Materials, And Methods Of Forming Memory Cells - Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material. | 07-15-2010 |
20110133268 | Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones. | 06-09-2011 |
20110147827 | Flash memory with partially removed blocking dielectric in the wordline direction - The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction. | 06-23-2011 |
20110220989 | Memory Cells, Methods Of Forming Dielectric Materials, And Methods Of Forming Memory Cells - Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material. | 09-15-2011 |
20120161318 | MULTILAYER DIELECTRIC MEMORY DEVICE - A memory device has multiple dielectric barrier regions. A memory device has multiple barrier regions that provide higher or lower current-voltage slope compared to a memory device having a single barrier region. The device also has electrode regions that provide further control over the current-voltage relationship. | 06-28-2012 |
20140091429 | MULTILAYER DIELECTRIC MEMORY DEVICE - A memory device has multiple dielectric barrier regions. A memory device has multiple barrier regions that provide higher or lower current-voltage slope compared to a memory device having a single barrier region. The device also has electrode regions that provide further control over the current-voltage relationship. | 04-03-2014 |
20140148002 | NANOCRYSTAL FORMATION USING ATOMIC LAYER DEPOSITION - Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures. | 05-29-2014 |
20140239369 | SELF-ALIGNED CHARGE-TRAPPING LAYERS FOR NON-VOLATILE DATA STORAGE, PROCESSES OF FORMING SAME, AND DEVICES CONTAINING SAME - A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device. | 08-28-2014 |
Patent application number | Description | Published |
20090204068 | AGENT DELIVERY CATHETER HAVING AN INFLATION BRIDGE BETWEEN TWO AXIALLY SPACED BALLOONS - An agent delivery catheter having two or more axially spaced balloons and an inflation bridge providing fluid communication between the two balloons. The catheter generally has a proximal balloon, a distal balloon, and a tube defining an inflation bridge lumen which is located in part within the inflatable interiors of the balloons, and which extends therebetween, and which has a proximal port within the proximal balloon interior and a distal port within the distal balloon interior to thereby provide for inflation of the distal balloon by placing the distal balloon interior in fluid communication with the proximal balloon interior of the shaft. | 08-13-2009 |
20100145265 | AGENT DELIVERY CATHETER HAVING A RADIALLY EXPANDABLE CENTERING SUPPORT MEMBERS - A catheter for delivering an agent to an injection site in a wall of a patient's body lumen, with an elongated shaft having a needle-through lumen slidably containing a needle therein, and an expandable member on the distal shaft section which has a collapsed configuration and a radially expanded configuration. In the radially expanded configuration, the expandable member supports the shaft in a position spaced away from the body lumen wall, and the needle slidably exits the needle-through lumen in the extended configuration through the port spaced away from the body lumen wall as a portion of the expandable member maintains the position of the port section of the shaft in the body lumen. The expandable member typically has an open-walled, helical, or lobed configuration providing a perfusion path along the expandable member. | 06-10-2010 |
20120143139 | AGENT DELIVERY CATHETER HAVING A RADIALLY EXPANDABLE CENTERING SUPPORT MEMBER - A catheter for delivering an agent to an injection site in a wall of a patient's body lumen, with an elongated shaft having a needle-through lumen slidably containing a needle therein, and an expandable member on the distal shaft section which has a collapsed configuration and a radially expanded configuration. In the radially expanded configuration, the expandable member supports the shaft in a position spaced away from the body lumen wall, and the needle slidably exits the needle-through lumen in the extended configuration through the port spaced away from the body lumen wall as a portion of the expandable member maintains the position of the port section of the shaft in the body lumen. The expandable member typically has an open-walled, helical, or lobed configuration providing a perfusion path along the expandable member. | 06-07-2012 |
20140121603 | AGENT DELIVERY CATHETER HAVING RADIALLY EXPANDABLE CENTERING SUPPORT MEMBER - A catheter for delivering an agent to an injection site in a wall of a patient's body lumen, with an elongated shaft having a needle-through lumen slidably containing a needle therein, and an expandable member on the distal shaft section which has a collapsed configuration and a radially expanded configuration. In the radially expanded configuration, the expandable member supports the shaft in a position spaced away from the body lumen wall, and the needle slidably exits the needle-through lumen in the extended configuration through the port spaced away from the body lumen wall as a portion of the expandable member maintains the position of the port section of the shaft in the body lumen. The expandable member typically has an open-walled, helical, or lobed configuration providing a perfusion path along the expandable member. | 05-01-2014 |
Patent application number | Description | Published |
20130178751 | IMPLANTABLE MEDICAL DEVICE FOR MEASURING PRESSURE VIA AN L-C RESONANT CIRCUIT - An implantable medical device controls the excitation of and processes signals received from passive pressure sensor components of an implantable lead. The passive pressure sensor components include an inductor-capacitor (L-C) resonant circuit that has a resonant frequency that corresponds in some aspects to the pressure external to the implantable lead. The capacitive circuit portion of the resonant circuit may be flexible such that changes in pressure at the capacitive circuit cause changes in the capacitance of the capacitive circuit. Thus, changes in pressure at the pressure sensor are reflected by changes in the resonant frequency of the excited resonant circuit. The L-C resonant circuit is excited by a signal coupled to the L-C resonant circuit by the implantable medical device. In some embodiments, the implantable medical device receives such an excitation signal from an external device. In some embodiments, the implantable medical device generates the excitation signal. | 07-11-2013 |
20140094889 | IMPLANTABLE THERAPY LEAD WITH CONDUCTOR CONFIGURATION ENHANCING ABRASION RESISTANCE - An implantable therapy lead employs electrical conductors configured to enhance the abrasion resistance of the lead. Specifically, conductors are configured to create a surface contact area with walls of a wall lumen of a tubular body that is greater than would otherwise be possible with traditional conductors that have a circular transverse cross-section. As a result, the abrasion pressure of the conductors against the lumen walls is decreased for the conductors disclosed herein as compared to that of traditional conductors. | 04-03-2014 |
20140094890 | IMPLANTABLE THERAPY LEAD WITH CONDUCTOR CONFIGURATION ENHANCING ABRASION RESISTANCE - An implantable therapy lead employs electrical conductors configured to enhance the abrasion resistance of the lead. Specifically, conductors are configured to create a surface contact area with walls of a wall lumen of a tubular body that is greater than would otherwise be possible with traditional conductors that have a circular transverse cross-section. As a result, the abrasion pressure of the conductors against the lumen walls is decreased for the conductors disclosed herein as compared to that of traditional conductors. | 04-03-2014 |
20140100627 | LEADLESS INTRA-CARDIAC MEDICAL DEVICE WITH INTEGRATED L-C RESONANT CIRCUIT PRESSURE SENSOR - A leadless intra-cardiac medical device comprises an integrated L-C resonant circuit pressure sensor. In some embodiments, the pressure sensor comprises a passive sensor that measures pressure in response to an externally generated excitation signal. In some embodiments, the pressure sensor comprises an active sensor that measures pressure in response to an internally generated excitation signal. | 04-10-2014 |
20140107723 | SINGLE-CHAMBER LEADLESS INTRA-CARDIAC MEDICAL DEVICE WITH DUAL-CHAMBER FUNCTIONALITY - A leadless implantable medical device (LIMD) comprises a housing configured to be implanted entirely within a single local ventricular chamber of the heart near a local apex region. A base on the housing is configured to be secured to tissue of interest, while a distal electrode is provided on the base and extends outward such that, when the device is implanted in the local chamber, the distal electrode is configured to engage the distal apex region at a distal activation site within the conduction network of the adjacent ventricular chamber. | 04-17-2014 |
20140172034 | INTRA-CARDIAC IMPLANTABLE MEDICAL DEVICE WITH IC DEVICE EXTENSION FOR LV PACING/SENSING - An assembly is provided for introducing a device within a heart of a patient. The assembly is comprised of a sheath having at least one internal passage. An intra-cardiac implantable medical device (IIMD) is retained within the at least one internal passage, wherein the IIMD is configured to be discharged from a distal end of the sheath. The IIMD has a housing with a first active fixation member configured to anchor the IIMD at a first implant location within a local chamber of the heart. | 06-19-2014 |
20140172060 | METHOD OF IMPLANTING A SINGLE-CHAMBER LEADLESS INTRA-CARDIAC MEDICAL DEVICE WITH DUAL-CHAMBER FUNCTIONALITY AND SHAPED STABILIZATION INTRA-CARDIAC EXTENSION - A leadless intra-cardiac medical device (LIMD) is configured to be implanted entirely within a heart of a patient. The LIMD comprises a housing configured to be securely attached to an interior wall portion of a chamber of the heart, and a stabilizing intra-cardiac (IC) device extension connected to the housing. The stabilizing IC device extension may include a stabilizer arm, and/or an appendage arm, or an elongated body or a loop member configured to be passively secured within the heart. | 06-19-2014 |
20140276125 | METHOD AND SYSTEM FOR CHARACTERIZING CARDIAC FUNCTION BASED ON DYNAMIC IMPEDANCE - A method and system are provided for characterizing cardiac function. The method and system comprise collecting cardiac signals associated with electrical or mechanical behavior of a heart over at least one cardiac cycle; identifying a timing feature of interest (FOI) from the cardiac signals; collecting dynamic impedance (DI) data over at least one cardiac cycle (CC), designated by the timing FOI, along at least one of i) a venous return (VR) vector or ii) a right ventricular function (RVF) vector; and analyzing at least one morphologic characteristic from the DI data based on at least one of i) a VR-DI correlation metric to obtain a VR indicator associated with the CC or ii) a RVF-DI correlation metric to obtain a RVF indicator associated with CC. | 09-18-2014 |
20140277259 | SYSTEMS AND METHODS FOR PROVIDING A DISTRIBUTED VIRTUAL STIMULATION CATHODE FOR USE WITH AN IMPLANTABLE NEUROSTIMULATION SYSTEM - Techniques are provided for controlling and delivering spinal cord stimulation (SCS) or other forms of neurostimulation. In one example, neurostimulation pulses are generated wherein successive pulses alternate in polarity so that a pair of electrodes alternate as cathodes. Each pulse has a cathodic amplitude sufficient to achieve cathodic capture of tissues adjacent the particular electrode used as the cathode for the pulse. The neurostimulation pulses are delivered to patient tissues using the electrodes to alternatingly capture tissues adjacent opposing electrodes via cathodic capture to achieve a distributed virtual stimulation cathode. Various pulse energy savings techniques are also set forth that exploit the distributed virtual stimulation cathode. | 09-18-2014 |
20140277278 | CLOSED-LOOP SYSTEMS AND METHODS FOR CONTROLLING NEUROSTIMULATION BASED ON FAR-FIELD CARDIAC SIGNALS SENSED BY A SPINAL CORD STIMULATION DEVICE - Techniques are provided for controlling spinal cord stimulation (SCS) or other forms of neurostimulation. Far-field cardiac electrical signals are sensed using a lead of the SCS device and neurostimulation is selectively delivering using a set of adjustable SCS control parameters. Parameters representative of cardiac rhythm are derived from the far-field cardiac electrical signals. The parameters representative of cardiac rhythm are correlated with SCS control parameters to thereby map neurostimulation control settings to cardiac rhythm parameters. The delivery of further neurostimulation is then controlled based on the mapping of neurostimulation control settings to cardiac rhythm parameters to, for example, address any cardiovascular disorders detected based on the far-field cardiac signals. In this manner, a closed loop control system is provided to automatically adjust SCS control parameters to respond to changes in cardiac rhythm such as changes associated with ischemia, arrhythmia or heart failure. | 09-18-2014 |
20150025397 | SYSTEM AND METHOD FOR ESTIMATING CARDIAC PRESSURE BASED ON CARDIAC ELECTRICAL CONDUCTION DELAYS USING AN IMPLANTABLE MEDICAL DEVICE - Techniques are provided for estimating left atrial pressure (LAP) or other cardiac performance parameters based on measured conduction delays. In particular, LAP is estimated based interventricular conduction delays. Predetermined conversion factors stored within the device are used to convert the various the conduction delays into LAP values or other appropriate cardiac performance parameters. The conversion factors may be, for example, slope and baseline values derived during an initial calibration procedure performed by an external system, such as an external programmer. In some examples, the slope and baseline values may be periodically re-calibrated by the implantable device itself. Techniques are also described for adaptively adjusting pacing parameters based on estimated LAP or other cardiac performance parameters. Still further, techniques are described for estimating conduction delays based on impedance or admittance values and for tracking heart failure therefrom. | 01-22-2015 |
20150051661 | Method and System for Validating Local Capture in Multisite Pacing Delivery - A method for use with an implantable system including a lead having multiple electrodes implantable proximate to a patient's left ventricular (LV) chamber includes simultaneously delivering pacing pulses over corresponding pacing vectors defined by electrodes proximate to the LV chamber. The method includes recording evoked responses responsive to the pacing pulses that are measured over separate corresponding sensing channels. The method also includes comparing the evoked responses to a template that represents local capture of a local LV tissue region along one or more of the corresponding pacing vectors. The comparison is used to determine whether the pacing pulses achieved local capture along the corresponding pacing vectors. At least one of the pacing pulses or pacing vectors are updated based on the comparison of the evoked responses to the template in order to determine a local capture threshold for the corresponding pacing vectors. | 02-19-2015 |
20150057716 | METHODS AND SYSTEMS FOR ANALYZING VALVE RELATED TIMING AND MONITORING HEART FAILURE - A method and system are provided to analyze valve related timing and monitor heart failure. The method and system comprise collecting cardiac signals associated with an atrial chamber of interest; collecting dynamic impedance (DI) data along an atria-function focused (AFF) vector to form a DI data set, the DI data set including information corresponding to a mechanical function (MF) of a valve associated with the atrial chamber of interest; identifying, from the cardiac signals, an intra-atrial conduction timing (IACT) associated with the atrial chamber of interest; estimating an MF landmark at which the mechanical function of the valve occurs based on the DI data set; analyzing a timing delay between the MF landmark and the IACT; and adjusting a therapy, based on the timing delay, to encourage atrial contribution to ventricular filling. | 02-26-2015 |
20150073287 | METHOD AND SYSTEM FOR CHARACTERIZING CHAMBER SPECIFIC FUNCTION - A method and system are provided for characterizing chamber specific function. The method and system comprise collecting cardiac signals associated with asynchronous timing between first and second chambers of the heart; collecting dynamic impedance (DI) data along a chamber-specific function (CSF) vector to form a DI data set, the DI data set collected during a collection window that is temporally aligned based on a timing feature of interest (FOI); repeating the collection operations over multiple cardiac cycles (CC) to obtain an ensemble of DI data sets; and combining the ensemble of DI data sets to form a composite DI data set that is coupled to a chamber functional mechanic of interest (FMOI) associated with the first chamber and decoupled from functional mechanics associated with the second chamber; and analyzing the composite DI data set to obtain a CSF indicator associated with the chamber FMOI of the first chamber. | 03-12-2015 |
20150142010 | NEUROSTIMULATION LEADS HAVING TWO-DIMENSIONAL ARRAYS - A neurostimulation lead including an elongated lead body having a distal end and a proximal base. The lead body may have an elastic property such that the lead body is capable of flexing between different geometries. The lead may also include electrodes positioned along the lead body. The lead body may be configured to be straightened into a substantially linear geometry for delivering the lead body into an epidural space and may be biased such that the lead body is configured to have a wave-like geometry when disposed within the epidural space. The lead body may form first and second lateral segments that are joined by a corresponding linking portion when in the wave-like geometry. | 05-21-2015 |
20150142071 | SYSTEMS AND METHODS FOR DETERMINING OPTIMAL INTERVENTRICULAR PACING DELAYS BASED ON ELECTROMECHANICAL DELAYS - Techniques are provided for use with implantable medical devices such as pacemakers for optimizing interventricular (VV) pacing delays for use with cardiac resynchronization therapy (CRT). In one example, ventricular electrical depolarization events are detected within a patient in whom the device is implanted. The onset of isovolumic ventricular mechanical contraction is also detected based on cardiomechanical signals detected by the device, such as cardiogenic impedance (Z) signals, S1 heart sounds or left atrial pressure (LAP) signals. Then, an electromechanical time delay (T_QtoVC) between ventricular electrical depolarization and the onset of isovolumic ventricular mechanical contraction is determined. VV pacing delays are set to minimize the time delay to the onset of isovolumic ventricular mechanical contraction. Various techniques for identifying the onset of isovolumic ventricular contraction based on Z, S1 or LAP or other cardiomechanical signals are described. In some examples, CRT nonresponders are specifically identified and/or heart failure progression is tracked. | 05-21-2015 |
20150142072 | SYSTEMS AND METHODS FOR DETERMINING OPTIMAL INTERVENTRICULAR PACING DELAYS BASED ON ELECTROMECHANICAL DELAYS - Techniques are provided for use with implantable medical devices such as pacemakers for optimizing interventricular (VV) pacing delays for use with cardiac resynchronization therapy (CRT). In one example, ventricular electrical depolarization events are detected within a patient in whom the device is implanted. The onset of isovolumic ventricular mechanical contraction is also detected based on cardiomechanical signals detected by the device, such as cardiogenic impedance (Z) signals, S1 heart sounds or left atrial pressure (LAP) signals. Then, an electromechanical time delay (T_QtoVC) between ventricular electrical depolarization and the onset of isovolumic ventricular mechanical contraction is determined. VV pacing delays are set to minimize the time delay to the onset of isovolumic ventricular mechanical contraction. Various techniques for identifying the onset of isovolumic ventricular contraction based on Z, S1 or LAP or other cardiomechanical signals are described. In some examples, CRT nonresponders are specifically identified and/or heart failure progression is tracked. | 05-21-2015 |
20150202431 | MULTI-PIECE DUAL-CHAMBER LEADLESS INTRA-CARDIAC MEDICAL DEVICE AND METHOD OF IMPLANTING SAME - A leadless intra-cardiac medical device (LIMD) includes an electrode assembly configured to be anchored within a first wall portion of a first chamber of a heart. The electrode assembly includes an electrode main body having a first securing helix, an electrode wire segment extending from the body, and a first segment-terminating contact positioned on the electrode wire segment. The device further includes a housing assembly configured to be anchored within a second wall portion of a second chamber of the heart. The housing assembly includes a body having a second securing helix, a housing wire segment extending from the body, and a second segment-terminating contact positioned on the housing wire segment. The device also includes a connector block that electrically connects the electrode wire segment to the housing wire segment by retaining the first and second segment-terminating contacts. | 07-23-2015 |
20150224318 | METHODS AND SYSTEMS FOR NEUROSTIMULATION USING PADDLE LEAD - The present disclosure provides systems and methods for neurostimulation. The system includes a paddle including a plurality of electrodes arranged in a plurality of rows and columns, and an implantable pulse generator (IPG) electrically coupled to the paddle. The IPG is configured to step the paddle through a plurality of electrode configurations, wherein for each of the plurality of electrode configurations, a pair of electrodes in one row operate as anodes, and at least one electrode in the same row as the pair of electrodes and positioned between the pair of electrodes operates as a cathode. | 08-13-2015 |
20150265841 | LEADLESS SPINAL CORD STIMULATION SYSTEM AND METHOD INCLUDING SAME - A leadless neurostimulation (NS) device and method to manufacture the device is described. The leadless NS device has a first sub-unit (FU) and a second sub-unit (SU) separately and individually hermetically sealed. The FU and SU also include a flexible inter-connect that physically interconnects the FU and SU to one another. The leadless NS device also includes electrodes provided along the exterior surface of at least one of the first and second sub-units. The electrodes are configured to interface with nervous tissue in an epidural space of a patient and deliver stimulation pulses along the nervous tissue. At least partially housed within the FU includes a first subset of a power source, an energy management components, an electronics sub-system and telemetry component. Further, a second subset of the power source, energy management components, electronics sub-system and telemetry component are at least partially housed within the SU. | 09-24-2015 |
20150290461 | METHODS AND SYSTEMS FOR MONITORING ELECTRICAL STIMULATION USING PADDLE LEAD - The present disclosure provides systems and methods for neurostimulation. The method includes applying electrical stimulation to a patient using a paddle lead that includes a plurality of electrodes, acquiring evoked response data using at least some of the plurality of electrodes, wherein the evoked response data is indicative of a patient response to the electrical stimulation, transmitting the evoked response data to a computing device, and processing the evoked response data using the computing device to facilitate monitoring the applied electrical stimulation. | 10-15-2015 |