Tejas
Tejas Bhandare, Fremont, CA US
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20150023359 | EDGE EXTENSION OF AN ETHERNET FABRIC SWITCH - An apparatus, in one embodiment, includes an edge adaptor module, a storage device, and an encapsulation module. The edge adaptor module maintains a membership in a fabric switch. A fabric switch includes a plurality of switches and operates as a single switch. The storage device stores a first table comprising a first mapping between a first edge identifier and a switch identifier. The first edge identifier is associated with the edge adaptor module and the switch identifier is associated with a local switch. This local switch is a member of the fabric switch. The storage device also stores a second table comprising a second mapping between the first edge identifier and a media access control (MAC) address of a local device. During operation, the encapsulation module encapsulates a packet in a fabric encapsulation with the first edge identifier as the ingress switch identifier of the encapsulation header. | 01-22-2015 |
Tejas Gunjikar, Nashik - Maharashtra IN
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20130123179 | FAST DISSOLVING PHARMACEUTICAL COMPOSITION - The subject invention is directed to a pharmaceutical composition comprising an open matrix network carrying a pharmaceutically active ingredient, wherein the open matrix network comprises levan. | 05-16-2013 |
20130310319 | FAST DISSOLVING PHARMACEUTICAL COMPOSITION - The subject invention is directed to a pharmaceutical composition comprising an open matrix network carrying a pharmaceutically active ingredient, wherein the open matrix network comprises levan. | 11-21-2013 |
20150150798 | FAST DISSOLVING PHARMACEUTICAL COMPOSITION - The subject invention is directed to a pharmaceutical composition comprising an open matrix network carrying a pharmaceutically active ingredient, wherein the open matrix network comprises levan. | 06-04-2015 |
Tejas Gunjikar, Nashik-Pune Hwy IN
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20150045300 | FAST DISSOLVING PHARMACEUTICAL COMPOSITION - The subject invention is directed to a pharmaceutical composition comprising an open matrix network carrying a pharmaceutically active ingredient, wherein the open matrix network comprises both the polysaccharides levan and inulin. | 02-12-2015 |
Tejas Gunjikar, Nashik IN
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20130123180 | FAST DISSOLVING PHARMACEUTICAL COMPOSITION - The subject invention is directed to a pharmaceutical composition comprising an open matrix network carrying a pharmaceutically active ingredient, wherein the open matrix network comprises inulin. | 05-16-2013 |
Tejas Jukar, Fremont, CA US
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20150023161 | MODIFYING SYSTEM TIMERS FOR OPTIMIZING MOBILE TRAFFIC MANAGEMENT - Systems and methods for optimizing mobile traffic management are disclosed. In a mobile device, network stack timers or protocol stack timers are modified to extend delay tolerance of applications for radio alignment. In an embodiment, using a variable gating delay, that takes into consideration the delay tolerance of applications that is extended and other information such as radio state information, are used to align and transfer outgoing traffic from multiple applications to one or more application servers, receive requests and/or responses from one or more application servers or a carrier-side proxy server to minimize the number of times the mobile device connects to the network, reducing the power consumption on the mobile device and unnecessary signaling in the network. | 01-22-2015 |
20150023162 | EXTENDING DELAY TOLERANCE OF MOBILE APPLICATIONS FOR OPTIMIZING MOBILE TRAFFIC MANAGEMENT - Systems and methods for extending delay tolerance of mobile applications to optimize mobile traffic management are disclosed. In a mobile device, network stack timers or protocol stack timers are modified to extend delay tolerance of applications for radio alignment. In an embodiment, tolerance of mobile applications on a mobile device to delay in establishing a connection to a wireless network is extended by an application or a local proxy on a mobile device. Based on the tolerance that is extended, requests intercepted from the mobile applications are aggregated, over a period of time, such that transfer of the requests intercepted during the period of time is delayed. This minimizes the number of times the mobile device connects to the network, reducing the power consumption on the mobile device and unnecessary signaling in the network. | 01-22-2015 |
Tejas Jukar, San Carlos, CA US
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20150055463 | MODIFYING SYSTEM TIMERS FOR OPTIMIZING MOBILE TRAFFIC MANAGEMENT - A mobile device for optimizing mobile traffic is provided. The device includes a radio. The mobile device is configured to modify system timers to increase tolerance to delay in establishing a connection to the wireless network, intercept requests to establish a connection to a wireless network, wherein the requests correspond to non-user interactive traffic, accumulate the requests that are intercepted over a period of time, and transfer the requests that are accumulated over the wireless network at the end of the period of time. | 02-26-2015 |
20150109914 | MODIFYING SYSTEM TIMERS FOR OPTIMIZING MOBILE TRAFFIC MANAGEMENT - A computer-readable storage medium storing instructions that when executed by a processor is provided. The instructions cause the processor to intercept requests from mobile applications on a mobile device, modify system timers to extend delay tolerance impacting the mobile applications, and bundle the requests that are intercepted for radio alignment. Associated methods are also provided. | 04-23-2015 |
Tejas Karandakar, Redmond, WA US
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20110296234 | VIRTUAL MACHINE I/O MULTIPATH CONFIGURATION - Disclosed are methods for exposing multiple interfaces of a communications fabric (Ethernet, FibreChannel, Serial-Attached-SCSI, Infiniband, etc.) of a virtual machine and automatically mapping those interfaces onto separate physical interfaces. Such an approach may preserve the simple management experience of a single connection point into the virtual machine while allowing the OS and application within the virtual machine to supply information necessary to efficiently use the multiply underlying physical links. | 12-01-2011 |
Tejas Karkhanis, White Plains, NY US
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20110320765 | VARIABLE WIDTH VECTOR INSTRUCTION PROCESSOR - A computer processor, method, and computer program product for executing vector processing instructions on a variable width vector register file. An example embodiment is a computer processor that includes an instruction execution unit coupled to a variable width vector register file which contains a number of vector registers, the width of the vector registers is changeable during operation of the computer processor. | 12-29-2011 |
20130268741 | POWER REDUCTION IN SERVER MEMORY SYSTEM - A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests. | 10-10-2013 |
20150032997 | TRACKING LONG GHV IN HIGH PERFORMANCE OUT-OF-ORDER SUPERSCALAR PROCESSORS - Tracking global history vector in high performance out of order superscalar processors, in one aspect, may comprise providing a shift register storing global history vector that stores branch predictions and outcomes. A counter is maintained to determine a number of bits to shift the shift register to recover branch history. In another aspect, the global history vector may be implemented with a circular buffer structure. Youngest and oldest pointers to the circular buffer are maintained and used in recovery. | 01-29-2015 |
20150046690 | Techinques for selecting a predicted indirect branch address from global and local caches - A technique for branch target prediction includes storing, based on an instruction fetch address for a group of fetched instructions, first predicted targets for first indirect branch instructions in respective entries of a local count cache. Second predicted targets for second indirect branch instructions are stored in respective entries of a global count cache, based on the instruction fetch address and a global history vector for the instruction fetch address. One of the local count cache and the global count cache is selected to provide a selected predicted target for an indirect branch instruction in the group of fetched instructions. | 02-12-2015 |
20150186145 | Compressed Indirect Prediction Caches - Provided herein is a compressed cache design to predict indirect branches in a microprocessor based on the characteristics of the addresses of the branch instructions. In one aspect, a method for predicting a branch target T in a microprocessor includes the following steps. A compressed count cache table (CTABLE) of branch targets indexed using a function combining a branch address and a branch history vector for each of the targets is maintained, wherein entries in the CTABLE contain only low-order bits of each of the targets in combination with an index bit(s) I. A given one of the entries is obtained related to a given one of the branch targets and it is determined from the index bits I whether A) high-order bits of the target are equal to the branch address, or B) the high-order bits of the target are contained in an auxiliary cache table (HTABLE). | 07-02-2015 |
20150363201 | PREDICTING INDIRECT BRANCHES USING PROBLEM BRANCH FILTERING AND PATTERN CACHE - Predicting indirect branch instructions may comprise predicting a target address for a fetched branch instruction. Accuracy of the target address may be tracked. The fetched branch instruction may be flagged as a problematic branch instruction based on the tracking. A pattern cache may be trained for predicting more accurate target address for the fetched branch instruction, and the next time the fetched branch instruction is again fetched, a target address may be predicted from the pattern cache. | 12-17-2015 |
Tejas Kokje, San Jose, CA US
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20100310253 | LESS LOSS IN-ORDER DELIVERY PROTOCOL FOR FIBRE CONNECTION ARCHITECTURE - Methods and apparatus for providing in-order delivery in Fibre Channel (FC) fabric are disclosed. A topological change between a first switch and a second switch is evaluated to determine whether the topological change may result in out-of-order delivery. If it is determined that the topological change may result in out-of-order delivery, a flush frame is sent to the second switch and stop-on-mark is performed on all interfaces of affected links. Upon receiving the flush frame, the second switch drains all virtual output queues (VOQs) and sends an acknowledgement frame to the first switch. The first switch resumes in-order-delivery in an affected link after receiving the acknowledgement frame or expiration of a lifetime time of a frame. | 12-09-2010 |
Tejas Kokje, Santa Clara, CA US
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20090207737 | REDUCING PACKET DROPS IN NETWORKS GUARANTEEING IN-ORDER DELIVERY - In one embodiment, the convergence node switches of a destination node switch in a network having multiple equal paths between a source switch and destination switch are identified. When a new equal cost path is added to the network, packets are flushed up to the convergence node switch closest to the source switch. | 08-20-2009 |
20100027427 | Hop cost as secondary metric for equal cost multi-paths - Systems, methods, and other embodiments associated with computing path costs based on link cost as a primary metric and hop cost as a secondary metric are presented. The secondary metric facilitates distinguishing between what would be equal cost multi-paths if only link cost was employed. One example method includes computing a modified link cost for a plurality of paths between switches. The example method may also include determining a lowest modified link cost associated with a path between the switches. The example method may also include providing a signal identifying the lowest modified link cost. | 02-04-2010 |
Tejas Kokje, Milpitas, CA US
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20140119372 | OTV SCALING: SITE VIRTUAL MAC ADDRESS - Techniques for providing an extended layer 2 network. Embodiments receive, at a first network device in a first layer 2 network within the extended layer 2 network, a data packet specifying a destination Media Access Control (MAC) address. Upon determining that the destination MAC address is a site virtual MAC (S-VMAC) address, the data packet is forwarded to a second network device in a second layer 2 network within the extended layer 2 network and associated with the S-VMAC address, where the second network device is configured to determine a second destination MAC address for the data packet based on an Internet Protocol (IP) address specified in the data packet, and is further configured to forward the data packet to a destination device associated with the determined second destination MAC address. | 05-01-2014 |
Tejas Krishnamohan, Mountain View, CA US
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20110133268 | Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones. | 06-09-2011 |
20110147827 | Flash memory with partially removed blocking dielectric in the wordline direction - The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction. | 06-23-2011 |
20120327713 | IN-FIELD BLOCK RETIRING - Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed. | 12-27-2012 |
20130332769 | IN-FIELD BLOCK RETIRING - Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed. | 12-12-2013 |
Tejas Krishnamohan, Palo Alto, CA US
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20090001443 | NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC - Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed. | 01-01-2009 |
20090097320 | Memory Cells, Electronic Systems, Methods Of Forming Memory Cells, And Methods of Programming Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones. | 04-16-2009 |
20090283817 | FLOATING GATE STRUCTURES - Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon. | 11-19-2009 |
20090321809 | GRADED OXY-NITRIDE TUNNEL BARRIER - Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed. | 12-31-2009 |
Tejas Mayavanshi, Bloomington, IL US
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20110146600 | METHOD OF COOLING A HIGH PRESSURE PLUNGER - A pumping element for pressurizing a fluid within a fluid pump includes a plunger reciprocally disposed within a bore defined in a pump housing. The plunger and housing at least partially define a pressurization chamber into which fluid is pressurized. A flow path is defined between the plunger and the bore, the flow path permitting fluid to pass from the pressurization chamber during pressurization of fluid disposed therein. A weep annulus is formed between the plunger and the bore, the weep annulus being disposed adjacent to the bore and being part of a cooling circuit for the pumping element. The housing further defines cooling and drain passages which are in fluid communication with one another via the weep annulus. The plunger an bore are convectively cooled when cooling fluid is supplied to the weep annulus via the cooling passage and drained away via the drain passage. | 06-23-2011 |
Tejas Ravani, San Diego, CA US
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20160043775 | NEAR FIELD COMMUNICATION MODE ADJUSTMENT BASED ON A SCREEN STATE - The present aspects relate to adjusting an NFC mode based on a screen state indication, comprising receiving, at an NFC controller, an NFC controller interface (NCI) indication from a device host, wherein the NCI indication specifies a screen state of the device host, and adjusting one or more NFC modes at the NFC controller based on the NCI indication. | 02-11-2016 |
Tejas Shah, Schaumburg, IL US
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20140162762 | GAMING SYSTEM WITH PRIVACY FEATURES - A wagering game system includes a peripheral device with a peripheral device display and at least one processor configured to execute at least one application to display information on the peripheral device display. The system also includes a wagering game terminal with a terminal display configured to display a wagering game and a player-accessible interface configured to allow a player to communicatively couple the peripheral device to the wagering game terminal. The at least one application includes a wagering game application relating to the wagering game displayed on the terminal display of the wagering game terminal, and the at least one processor of the peripheral device executes the wagering application to display, on the peripheral device display, wagering game information relating to the wagering game. | 06-12-2014 |
Tejas Tayade, Pune IN
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20140036699 | METHODS AND STRUCTURE FOR REDUCED LAYOUT CONGESTION IN A SERIAL ATTACHED SCSI EXPANDER - Methods and structure for reduced layout congestion in a switching device integrated circuit. A switching device such as a Serial Attached SCSI (SAS) expander comprises a switching circuit to couple any of a plurality (āNā) of physical links of the switching device with any other physical link of the switching device. The switching circuit comprises a first stage circuit adapted to couple any of the N physical links with a selected one of N/2 communication paths of the switching circuit and comprises a second stage circuit adapted to couple any of the N/2 communication paths with any of the N physical links. Since only N/2 communication paths may be active at any time in such a switching device, a control unit of the switching device tracks which of the N/2 communication paths are presently in use or unused so that an unused path may be selected for a new connection. | 02-06-2014 |