Patent application number | Description | Published |
20090001424 | III-nitride power device - A III-nitride power device that includes a Schottky electrode surrounding one of the power electrodes of the device. | 01-01-2009 |
20090189187 | Active area shaping for Ill-nitride device and process for its manufacture - A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. | 07-30-2009 |
20090278198 | Deep source electrode MOSFET - A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches. | 11-12-2009 |
20100006895 | III-NITRIDE SEMICONDUCTOR DEVICE - A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and a gate electrode that does not overlap the top surface of the field dielectric bodies and is disposed over a well in the III-nitride heterojunction. | 01-14-2010 |
20100258841 | BACK DIFFUSION SUPPRESSION STRUCTURES - An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer. | 10-14-2010 |
20100258842 | ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR WITH IMPROVED GATE CHARACTERISTICS - An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 Å to 900 Å. In a preferred embodiment, the thickness is 600 Å. | 10-14-2010 |
20100258843 | ENHANCEMENT MODE GaN HEMT DEVICE AND METHOD FOR FABRICATING THE SAME - An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process. | 10-14-2010 |
20100258844 | BUMPED, SELF-ISOLATED GaN TRANSISTOR CHIP WITH ELECTRICALLY ISOLATED BACK SURFACE - A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device. | 10-14-2010 |
20100258848 | COMPENSATED GATE MISFET AND METHOD FOR FABRICATING THE SAME - A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer. | 10-14-2010 |
20110241019 | III-Nitride Power Semiconductor Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 10-06-2011 |
20110244671 | Method for Fabricating a III-Nitride Semiconductor Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 10-06-2011 |
20110248283 | VIA STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Semiconductor devices, such as GaN HEMT and HFET devices, and methods of forming such devices, with a via that provides an electrical connection between a contact and a corresponding external contact pad. Embodiments include semiconductor devices with a via extending through a dielectric material to connect a gate to a corresponding external contact pad, and semiconductor devices with a via extending through a dielectric material to connect an Ohmic contact and a corresponding external contact pad. Embodiments also include semiconductor devices with a via connecting an external contact pad to a gate that is formed above a dielectric material. | 10-13-2011 |
20120153300 | SEMICONDUCTOR DEVICES WITH BACK SURFACE ISOLATION - Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided. | 06-21-2012 |
20120175631 | ENHANCEMENT MODE GaN HEMT DEVICE WITH GATE SPACER AND METHOD FOR FABRICATING THE SAME - Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability. | 07-12-2012 |
20120193688 | ION IMPLANTED AND SELF ALIGNED GATE STRUCTURE FOR GaN TRANSISTORS - A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer. | 08-02-2012 |
20130105814 | Active Area Shaping for III-Nitride Devices | 05-02-2013 |
20130234153 | ENHANCEMENT MODE GaN HEMT DEVICE - An enhancement-mode GaN transistor. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process. | 09-12-2013 |
20130248884 | III-Nitride Power Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 09-26-2013 |
20140034959 | III-Nitride Semiconductor Device with Stepped Gate - A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. | 02-06-2014 |
20150028384 | GaN TRANSISTORS WITH POLYSILICON LAYERS FOR CREATING ADDITIONAL COMPONENTS - A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer. | 01-29-2015 |
20150028390 | GaN DEVICE WITH REDUCED OUTPUT CAPACITANCE AND PROCESS FOR MAKING SAME - A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor. | 01-29-2015 |
20150034962 | INTEGRATED CIRCUIT WITH MATCHING THRESHOLD VOLTAGES AND METHOD FOR MAKING SAME - An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess. | 02-05-2015 |