Patent application number | Description | Published |
20120301308 | GAS TURBINE COMPRESSOR LAST STAGE ROTOR BLADES WITH AXIAL RETENTION - A rotor blade and blade retention key assembly includes: a radially outer airfoil, a shank and a radially inner attachment dovetail. The attachment dovetail has a radially innermost surface formed with a notch at one axial end thereof, and a retention key is received in the notch, and rotatable from a retracted position where a retention key portion is substantially flush with the radially innermost surface, to an extended position where the retention key portion projects inwardly from said radially innermost surface and into a recess or pocket formed in a rotor wheel slot to prevent axial movement of the blade within the slot. | 11-29-2012 |
20130336777 | AIRFOIL SHAPE FOR A COMPRESSOR - An article of manufacture having a nominal airfoil profile substantially in accordance with Cartesian coordinate values of X, Y and Z set forth in a scalable table, the scalable table selected from the group of tables consisting of TABLES 1-11, wherein the Cartesian coordinate values of X, Y and Z are non-dimensional values convertible to dimensional distances by multiplying the Cartesian coordinate values of X, Y and Z by a number, and wherein X and Y are coordinates which, when connected by continuing arcs, define airfoil profile sections at each Z height, the airfoil profile sections at each Z height being joined with one another to form a complete airfoil shape. | 12-19-2013 |
20130336798 | AIRFOIL SHAPE FOR A COMPRESSOR - An article of manufacture having a nominal airfoil profile substantially in accordance with Cartesian coordinate values of X, Y and Z set forth in a scalable table, the scalable table selected from the group of tables consisting of TABLES 1-11, wherein the Cartesian coordinate values of X, Y and Z are non-dimensional values convertible to dimensional distances by multiplying the Cartesian coordinate values of X, Y and Z by a number, and wherein X and Y are coordinates which, when connected by continuing arcs, define airfoil profile sections at each Z height, the airfoil profile sections at each Z height being joined with one another to form a complete airfoil shape. | 12-19-2013 |
20140030098 | ARTICLE OF MANUFACTURE - An article of manufacture has a first component configured for use with a turbomachine. The first component is configured for attachment to a second component, and reduces the possibility of attachment with an undesired third component by modification of a. characteristic of the first component. This modification is matched by a complementary characteristic of the second component. The first component has a nominal airfoil profile substantially in accordance with Cartesian coordinate values of X, Y and Z set forth in a scalable table selected from the group consisting of TABLES 1-11. Cartesian coordinate values of X, Y and Z are non-dimensional values convertible to dimensional distances by multiplying by a number. X and Y are coordinates which, when connected by continuing arcs, define airfoil profile sections at each Z height. The airfoil profile sections at each Z height being joined with one another to form a complete airfoil shape. | 01-30-2014 |
Patent application number | Description | Published |
20120252232 | ELECTRICAL CONNECTOR - Electrical connectors that are mating compatible with the MicroTCA® standard and configured to be mounted to an underlying substrate are provided. Certain of the electrical connectors can be configured to be mounted to a substrate configured in accordance with the MicroTCA® press fit footprint. Additionally, electrical connectors that are mating compatible with the MicroTCA® standard and configured to be mounted to respective alternative footprints, and substrates configured in accordance with the respective alternative footprints are provided. The disclosed electrical connectors and corresponding substrate footprints can operate to transmit data at speed up to and in excess of 25 Gigabits per second. | 10-04-2012 |
20140182891 | GEOMETRICS FOR IMPROVING PERFORMANCE OF CONNECTOR FOOTPRINTS - In accordance with the various embodiments disclosed herein, an improved electrical connector footprint, such as on printed circuit boards (PCB), is described. For example, antipads can have a variety of sizes and pairs of differential signal traces can define centerlines that are spaced apart from each other. | 07-03-2014 |
20140310957 | ELECTRICAL CONNECTOR - Electrical connectors that are mating compatible with the MicroTCA® standard and configured to be mounted to an underlying substrate are provided. Certain of the electrical connectors can be configured to be mounted to a substrate configured in accordance with the MicroTCA® press fit footprint. Additionally, electrical connectors that are mating compatible with the MicroTCA® standard and configured to be mounted to respective alternative footprints, and substrates configured in accordance with the respective alternative footprints are provided. The disclosed electrical connectors and corresponding substrate footprints can operate to transmit data at speed up to and in excess of 25 Gigabits per second. | 10-23-2014 |
Patent application number | Description | Published |
20080206958 | ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN - The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer. | 08-28-2008 |
20080290379 | DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS - The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices. | 11-27-2008 |
20090121295 | METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES - Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET. | 05-14-2009 |
20090236640 | METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES - Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET. | 09-24-2009 |
20120104511 | DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS - The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices. | 05-03-2012 |
Patent application number | Description | Published |
20090053888 | Method of depositing a diffusion barrier layer which provides an improved interconnect - A method of depositing a duffusion barrier layer with overlying conductive layer or fill which lowers resistivity of a semiconductor device interconnect. The lower resistivity is achieved by inducing the formation of alpha tantalum within a tantalum-comprising barrier layer. | 02-26-2009 |
20090233438 | SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING - A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets. | 09-17-2009 |
20140305802 | SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING - A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets. | 10-16-2014 |
Patent application number | Description | Published |
20130280466 | Large Diameter, High Quality SiC Single Crystals, Method and Apparatus - A method and system of forming large-diameter SiC single crystals suitable for fabricating high crystal quality SiC substrates of 100, 125, 150 and 200 mm in diameter are described. The SiC single crystals are grown by a seeded sublimation technique in the presence of a shallow radial temperature gradient. During SiC sublimation growth, a flux of SiC bearing vapors filtered from carbon particulates is substantially restricted to a central area of the surface of the seed crystal by a separation plate disposed between the seed crystal and a source of the SiC bearing vapors. The separation plate includes a first, substantially vapor-permeable part surrounded by a second, substantially non vapor-permeable part. The grown crystals have a flat or slightly convex growth interface. Large-diameter SiC wafers fabricated from the grown crystals exhibit low lattice curvature and low densities of crystal defects, such as stacking faults, inclusions, micropipes and dislocations. | 10-24-2013 |
20130320275 | Vanadium Compensated, SI SiC Single Crystals of NU and PI Type and the Crystal Growth Process Thereof - In a crystal growth apparatus and method, polycrystalline source material and a seed crystal are introduced into a growth ambient comprised of a growth crucible disposed inside of a furnace chamber. In the presence of a first sublimation growth pressure, a single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a first gas that includes a reactive component that reacts with and removes donor and/or acceptor background impurities from the growth ambient during said sublimation growth. Then, in the presence of a second sublimation growth pressure, the single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a second gas that includes dopant vapors, but which does not include the reactive component. | 12-05-2013 |