Patent application number | Description | Published |
20090001371 | BLOCKING PRE-AMORPHIZATION OF A GATE ELECTRODE OF A TRANSISTOR - A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors. | 01-01-2009 |
20090001484 | REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS - By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions. | 01-01-2009 |
20090108295 | DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION - By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime. | 04-30-2009 |
20090108415 | INCREASING ETCH SELECTIVITY DURING THE PATTERNING OF A CONTACT STRUCTURE OF A SEMICONDUCTOR DEVICE - By forming an intermediate etch stop material or by appropriately positioning an additional etch stop material in a spacer structure of a polysilicon line, the probability of exposing a shallow doped region of an active semiconductor region during a critical contact etch step for forming rectangular contacts may be significantly reduced. Thus, leakage current, which may conventionally be created by etching into shallow doped regions during the contact etch step, may be reduced. | 04-30-2009 |
20090166618 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 07-02-2009 |
20090197381 | METHOD FOR SELECTIVELY FORMING STRAIN IN A TRANSISTOR BY A STRESS MEMORIZATION TECHNIQUE WITHOUT ADDING ADDITIONAL LITHOGRAPHY STEPS - A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps. | 08-06-2009 |
20090286389 | METHOD OF OPTIMIZING SIDEWALL SPACER SIZE FOR SILICIDE PROXIMITY WITH IN-SITU CLEAN - A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum. | 11-19-2009 |
20100078689 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET TO THE CHANNEL REGION - A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency. | 04-01-2010 |
20100155727 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 06-24-2010 |
20100164093 | HEAT DISSIPATION IN TEMPERATURE CRITICAL DEVICE AREAS OF SEMICONDUCTOR DEVICES BY HEAT PIPES CONNECTING TO THE SUBSTRATE BACKSIDE - By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions. | 07-01-2010 |
20100221906 | ENHANCING INTEGRITY OF A HIGH-K GATE STACK BY CONFINING A METAL CAP LAYER AFTER DEPOSITION - During a manufacturing sequence for forming a sophisticated high-k metal gate structure, a cover layer, such as a silicon layer, may be deposited on a metal cap layer in an in situ process in order to enhance integrity of the metal cap layer. The cover layer may provide superior integrity during the further processing, for instance in view of performing wet chemical cleaning processes and the subsequent deposition of a silicon gate material. | 09-02-2010 |
20100237431 | REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS - By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions. | 09-23-2010 |
20100244141 | THRESHOLD ADJUSTMENT OF TRANSISTORS INCLUDING HIGH-K METAL GATE ELECTRODE STRUCTURES COMPRISING AN INTERMEDIATE ETCH STOP LAYER - During the formation of sophisticated gate electrode structures, a replacement gate approach may be applied in which plasma assisted etch processes may be avoided. To this end, one of the gate electrode structures may receive an intermediate etch stop liner, which may allow the replacement of the placeholder material and the adjustment of the work function in a later manufacturing stage. The intermediate etch stop liner may not negatively affect the gate patterning sequence. | 09-30-2010 |
20100289083 | MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMATION IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE - In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced. | 11-18-2010 |
20100301421 | STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE - Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region. | 12-02-2010 |
20100301427 | WORK FUNCTION ADJUSTMENT IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY SELECTIVELY REMOVING A BARRIER LAYER - In a replacement gate approach in sophisticated semiconductor devices, a tantalum nitride etch stop material may be efficiently removed on the basis of a wet chemical etch recipe using ammonium hydroxide. Consequently, a further work function adjusting material may be formed with superior uniformity, while the efficiency of the subsequent adjusting of the work function may also be increased. Thus, superior uniformity, i.e., less pronounced transistor variability, may be accomplished on the basis of a replacement gate approach in which the work function of the gate electrodes of P-channel transistors and N-channel transistors is adjusted after completing the basic transistor configuration. | 12-02-2010 |
20100330757 | ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING A HARD MASK FOR OFFSET SPACER PATTERNING - When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure. | 12-30-2010 |
20110024805 | USING HIGH-K DIELECTRICS AS HIGHLY SELECTIVE ETCH STOP MATERIALS IN SEMICONDUCTOR DEVICES - A spacer structure in sophisticated semiconductor devices is formed on the basis of a high-k dielectric material, which provides superior etch resistivity compared to conventionally used silicon dioxide liners. Consequently, a reduced thickness of the etch stop material may nevertheless provide superior etch resistivity, thereby reducing negative effects, such as dopant loss in the drain and source extension regions, creating a pronounced surface topography and the like, as are typically associated with conventional spacer material systems. | 02-03-2011 |
20110024912 | CMOS DEVICE INCLUDING MOLECULAR STORAGE ELEMENTS IN A VIA LEVEL - Memory cells in integrated circuit devices may be formed on the basis of functional molecules which may be positioned within via openings on the basis of appropriate patterning techniques, which may also be used for forming semiconductor-based integrated circuits. Consequently, memory cells may be formed on a “molecular” level without requiring extremely sophisticated patterning regimes, such as electron beam lithography and the like. | 02-03-2011 |
20110024914 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE COMPRISING AN INTER-DIE CONNECTION ON THE BASIS OF FUNCTIONAL MOLECULES - In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips. | 02-03-2011 |
20110104863 | TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SACRIFICIAL CARBON SPACER - When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the dielectric cap layer of the gate electrode structures may be efficiently removed on the basis of a carbon spacer element, which may thus preserve the integrity of the silicon nitride spacer structure. Thereafter, the sacrificial carbon spacer may be removed substantially without affecting other device areas, such as isolation structures, active regions and the like, which may contribute to superior process conditions during the further processing of the semiconductor device. | 05-05-2011 |
20110129980 | CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL - Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a protective sidewall spacer structure, which in turn may result in superior uniformity of the threshold voltage of the transistors. The sacrificial fill material may be provided in the form of an organic material that may be reduced in thickness on the basis of a wet developing process, thereby enabling a high degree of process controllability. | 06-02-2011 |
20110159654 | ENHANCED CONFINEMENT OF HIGH-K METAL GATE ELECTRODE STRUCTURES BY REDUCING MATERIAL EROSION OF A DIELECTRIC CAP LAYER UPON FORMING A STRAIN-INDUCING SEMICONDUCTOR ALLOY - When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal. | 06-30-2011 |
20110186931 | SEMICONDUCTOR DEVICE FORMED BY A REPLACEMENT GATE APPROACH BASED ON AN EARLY WORK FUNCTION METAL - In a replacement gate approach, one work function metal may be provided in an early manufacturing stage, i.e., upon depositing the gate layer stack, thereby reducing the number of deposition steps required in a later manufacturing stage. Consequently, the further work function metal and the electrode metal may be filled into the gate trenches on the basis of superior process conditions compared to conventional replacement gate approaches. | 08-04-2011 |
20110230039 | DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION - By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime. | 09-22-2011 |
20110266625 | Maintaining Integrity of a High-K Gate Stack After Embedding a Stressor Material by Using a Liner - Gate failures in sophisticated high-k metal gate electrode structures formed in an early manufacturing stage may be reduced by forming a protective liner material after the incorporation of a strain-inducing semiconductor alloy and prior to performing any critical wet chemical processes. In this manner, attacks in the sensitive gate materials after the incorporation of the strain-inducing semiconductor material may be avoided, without influencing the further processing of the device. In this manner, very sophisticated circuit designs may be applied in sophisticated gate first approaches. | 11-03-2011 |
20110269277 | Reduced STI Topography in High-K Metal Gate Transistors by Using a Mask After Channel Semiconductor Alloy Deposition - In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate electrode structures may be reduced by providing a superior surface topography. To this end, the material loss in the isolation region may generally be reduced and a more symmetrical exposure to reactive etch atmospheres during the subsequent removal of the growth mask may be accomplished by providing an additional etch mask when removing the growth mask from the active regions of N-channel transistors, after the growth of the threshold adjusting semiconductor material on the active regions of the P-channel transistors. | 11-03-2011 |
20120028470 | Increasing Robustness of a Dual Stress Liner Approach in a Semiconductor Device by Applying a Wet Chemistry - In a dual stress liner approach, unwanted material provided between closely spaced gate electrode structures may be removed to a significant degree on the basis of a wet chemical etch process, thereby reducing the risk of creating patterning-related irregularities. Consequently, the probability of contact failures in sophisticated interlayer dielectric material systems formed on the basis of a dual stress liner approach may be reduced. | 02-02-2012 |
20120161243 | High-K Metal Gate Electrode Structures Formed by Cap Layer Removal Without Sacrificial Spacer - In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers. | 06-28-2012 |
20120196417 | Sophisticated Gate Electrode Structures Formed by Cap Layer Removal with Reduced Loss of Embedded Strain-Inducing Semiconductor Material - When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions. | 08-02-2012 |
20120211838 | Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas - When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy for | 08-23-2012 |
20120223309 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 09-06-2012 |
20130017679 | WORK FUNCTION ADJUSTMENT IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY SELECTIVELY REMOVING A BARRIER LAYER - Generally, the present disclosure is directed work function adjustment in high-k metal gate electrode structures. In one illustrative embodiment, a method is disclosed that includes removing a placeholder material of a first gate electrode structure and a second gate electrode structure, and forming a first work function adjusting material layer in the first and second gate electrode structures, wherein the first work function adjusting material layer includes a tantalum nitride layer. The method further includes removing a portion of the first work function adjusting material layer from the second gate electrode structure by using the tantalum nitride layer as an etch stop layer, removing the tantalum nitride layer by performing a wet chemical etch process, and forming a second work function adjusting material layer in the second gate electrode structure and above a non-removed portion of the first work function adjusting material layer in the first gate electrode structure. | 01-17-2013 |
20130130449 | STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE - Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region. | 05-23-2013 |
20130157450 | Methods of Forming Metal Silicide Regions on Semiconductor Devices - Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer. | 06-20-2013 |
20130221540 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE COMPRISING AN INTER-DIE CONNECTION ON THE BASIS OF FUNCTIONAL MOLECULES - In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips. | 08-29-2013 |
20130234213 | NISI REWORK PROCEDURE TO REMOVE PLATINUM RESIDUALS - The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C. | 09-12-2013 |
20130273729 | HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS IN TRANSISTORS OF DIFFERENT CONDUCTIVITY TYPE - In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence. | 10-17-2013 |
20130316511 | SUPERIOR STABILITY OF CHARACTERISTICS OF TRANSISTORS HAVING AN EARLY FORMED HIGH-K METAL GATE - When forming sophisticated transistors on the basis of a high-k metal gate electrode structure and a strain-inducing semiconductor alloy, a superior wet cleaning process strategy is applied after forming cavities in order to reduce undue modification of sensitive gate materials, such as high-k dielectric materials, metal-containing electrode materials and the like, and modification of a threshold voltage adjusting semiconductor alloy. Thus, the pronounced dependence of the threshold voltage of transistors of different width may be significantly reduced compared to conventional strategies. | 11-28-2013 |
20140011302 | SPACER FOR A GATE ELECTRODE HAVING TENSILE STRESS AND A METHOD OF FORMING THE SAME - By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor. | 01-09-2014 |
20140113419 | METHODS OF REDUCING MATERIAL LOSS IN ISOLATION STRUCTURES BY INTRODUCING INERT ATOMS INTO OXIDE HARD MASK LAYER USED IN GROWING CHANNEL SEMICONDUCTOR MATERIAL - In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process. | 04-24-2014 |
20140339604 | STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE - A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy. | 11-20-2014 |
20140353733 | PROTECTION OF THE GATE STACK ENCAPSULATION - Semiconductor device structures at advanced technologies are provided, wherein a reliable encapsulation of a gate dielectric is already formed during very early stages of fabrication. In illustrative embodiments, a gate stack is formed over a surface of a semiconductor substrate and a sidewall spacer is formed adjacent to the gate stack for covering sidewall surfaces of the gate stack. An additional thin layer is formed over the sidewall spacer, the gate stack and the surface of the semiconductor substrate, and thereafter source/drain extension regions are implanted through the additional thin layer into the substrate in alignment with the sidewall spacer. | 12-04-2014 |
20150031179 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING SILICIDED AND NON-SILICIDED CIRCUIT ELEMENTS - A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element. A first annealing process is performed, wherein an intrinsic stress is created at least in the first semiconductor material by stress memorization, and thereafter the first portion of the dielectric layer is removed. A layer of a metal is formed, and a second annealing process is performed, wherein the metal and the first semiconductor material react chemically to form a silicide. The second portion of the dielectric layer substantially prevents a chemical reaction between the second semiconductor material and the metal. | 01-29-2015 |