Patent application number | Description | Published |
20110096047 | DISPLAY DEVICE AND SEMICONDUCTOR DEVICE - An object is to detect reflected light from an object accurately and to improve accuracy of capturing an image in a photosensor included in a display panel. In the display panel including a photosensor, when an image of an object is captured, light is emitted from a light source to the object and reflected light enters the photosensor. In the case where the incident light is too strong with respect to sensitivity of the photosensor, luminance of the light source is lowered. In the case where the incident light is too weak with respect to sensitivity of the photosensor, the luminance of the light source is increased. | 04-28-2011 |
20110233555 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device for high power application which has good properties. A means for solving the above-described problem is to form a transistor described below. The transistor includes a source electrode layer; an oxide semiconductor layer in contact with the source electrode layer; a drain electrode layer in contact with the oxide semiconductor layer; a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate insulating layer in contact with an entire surface of the gate electrode layer. | 09-29-2011 |
20120033476 | INVERTER CIRCUIT, POWER CONVERTER CIRCUIT, AND ELECTRIC VEHICLE - An object is to reduce, with the control circuit of the full-bridge inverter circuit, distortions in an output signal of the inverter circuit resulting from an error in control of the switching of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit. The pulse width of a signal that controls ON/OFF of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit is reduced, i.e., the duty cycle of the signal is reduced. This results in a reduction in short-circuit periods during which both the high-side transistor and the low-side transistor are on, thereby reducing distortions in a signal. | 02-09-2012 |
20120140550 | INTEGRATED CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR DEVICE - An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop. | 06-07-2012 |
20120161139 | SEMICONDUCTOR CIRCUIT, METHOD FOR DRIVING THE SAME, STORAGE DEVICE, REGISTER CIRCUIT, DISPLAY DEVICE, AND ELECTRONIC DEVICE - A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily. | 06-28-2012 |
20120170355 | STORAGE ELEMENT, STORAGE DEVICE, AND SIGNAL PROCESSING CIRCUIT - A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read. | 07-05-2012 |
20120230138 | MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT - A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor. | 09-13-2012 |
20120268164 | PROGRAMMABLE LSI - A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off. | 10-25-2012 |
20120281455 | SEMICONDUCTOR DEVICE - A semiconductor device that has a simple peripheral circuit configuration, is unlikely to deteriorate due to repetitive data writing operations, and is used as a nonvolatile switch. Even when supply of a power supply voltage is stopped, data on a conduction state is held in a data retention portion connected to a thin film transistor including an oxide semiconductor layer having a channel formation region. The data retention portion is connected to a gate of a field-effect transistor in a current amplifier circuit (in which the field-effect transistor and a bipolar transistor are connected as a Darlington pair), and thus the conduction state is controlled without leaking charge in the data retention portion. | 11-08-2012 |
20120281456 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device includes: a memory circuit including a transistor including an oxide semiconductor in a semiconductor layer; a capacitor for storing electric charge for reading data retained in the memory circuit; a charge storage circuit for controlling storage of electric charge in the capacitor; a data detection circuit for controlling data reading; a timing control circuit for generating a first signal controlling storage of electric charge in the capacitor (storage is conducted with the charge storage circuit, and the first signal is generated with a second signal at a supply voltage and a third signal delayed from the second signal at the supply voltage in a period immediately after the supply of the supply voltage); an inverter circuit for outputting a potential obtained by inverting a potential of one electrode of the capacitor. | 11-08-2012 |
20120294080 | MEMORY DEVICE AND METHOD FOR DRIVING MEMORY DEVICE - A memory device according to the invention can be operated with a single potential, by which the use of a voltage converter can be excluded, leading to the reduction of power consumption. Such an operation can be achieved by utilizing capacitive coupling of a capacitor connected to a gate of a transistor for data writing. That is, the capacitive coupling is induced by inputting a signal, which is supplied by a delay circuit configured to delay a write signal having a potential equal to the power supply potential, to the capacitor. Increase in the potential of the gate by the capacitive coupling allows the transistor to be turned on in association with the power supply potential applied to the gate from a power supply. Data is written by inputting a signal having a potential equal to the power supply potential or a grounded potential to a node through the transistor. | 11-22-2012 |
20120311365 | PROGRAMMABLE LOGIC DEVICE - An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits. | 12-06-2012 |
20140048802 | Storage Element, Storage Device, And Signal Processing Circuit - A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read. | 02-20-2014 |
20140321180 | Inverter Circuit, Power Converter Circuit, And Electric Vehicle - An object is to reduce, with the control circuit of the full-bridge inverter circuit, distortions in an output signal of the inverter circuit resulting from an error in control of the switching of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit. The pulse width of a signal that controls ON/OFF of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit is reduced, i.e., the duty cycle of the signal is reduced. This results in a reduction in short-circuit periods during which both the high-side transistor and the low-side transistor are on, thereby reducing distortions in a signal. | 10-30-2014 |
20150048362 | SEMICONDUCTOR DEVICE - To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor. | 02-19-2015 |
20150070064 | INTEGRATED CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR DEVICE - An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop. | 03-12-2015 |
Patent application number | Description | Published |
20080211561 | Clock Signal Generation Circuit and Semiconductor Device - The semiconductor device is provided with a clock signal generation circuit that includes a reference clock signal generation circuit which generates a first reference clock signal, a first counter circuit which counts the number of rising edges of the first reference clock signal by using the first reference clock signal and a synchronizing signal, a second counter circuit which counts the number of rising edges of the first reference clock signal by using an enumerated value of the first counter circuit, a first divider circuit which divides a frequency of the first reference clock signal by using the enumerated value of the first counter circuit and generates a second reference clock signal, and a second divider circuit which divides a frequency of the second reference clock signal and generates a clock signal. | 09-04-2008 |
20080258793 | Clock generating circuit and semiconductor device provided with clock generating circuit - An object is to provide a clock generating circuit that can suppress variation of an oscillation frequency from the clock generating circuit, which is due to a change in the output voltage according to a discharging characteristic of the battery, and effectively utilize the remaining power of the battery. A structure includes an output voltage detecting circuit for detecting an output voltage from a battery; a frequency-division number determining circuit for determining the number of frequency-division by a value of the output voltage detected by the output voltage detecting circuit; an oscillation circuit for outputting a reference clock signal depending on the output voltage; a counter circuit for counting a number of waves of the reference clock signal that depends on the number of frequency-division; and a frequency-dividing circuit that frequency-divides the reference clock signal depending on the number of waves counted by the counter circuit. | 10-23-2008 |
20080265961 | CLOCK SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE - In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio. | 10-30-2008 |
20080266010 | Semiconductor device and driving method thereof - A low-power-consumption semiconductor device and a driving method thereof where a clock signal generation is controlled. A transmission and reception control circuit to control signal communication with an outside; a ring oscillator control circuit to detect an edge in a receiving signal and control a ring oscillator; a clock generation circuit to generate a clock signal based on the ring oscillator; and a logic circuit to operate based on a clock signal are included. During signal communication between the transmission and reception control circuit and the outside, the ring oscillator operates and a clock signal is output from the clock generation circuit when the ring oscillator control circuit detects an edge in a receiving signal, and the ring oscillator stops and output of the clock signal from the clock generation circuit stops when transmission of a reply signal from the transmission and reception control circuit to the outside is terminated. | 10-30-2008 |
20100045355 | CLOCK SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE - In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio. | 02-25-2010 |
20110057725 | SEMICONDUCTOR DEVICE - A semiconductor device such as an RFID, which can easily generate a given stable potential, is provided. Circuits included in a semiconductor device are categorized depending on whether a given stable power source potential is necessary. A power source potential generated from a wireless signal received by an antenna with the use of the antenna and a rectifier circuit is supplied to a circuit which needs a given stable power source potential through a regulator. On the other hand, a power source potential generated by the rectifier circuit is supplied to a circuit other than the circuit which needs the arbitrary power source potential. Thus, a semiconductor device including a regulator circuit easily designed with a smaller layout can be provided, and the semiconductor device can easily generate a given stable power source potential. | 03-10-2011 |
20110074801 | CONTROL CIRCUIT OF DISPLAY DEVICE, AND DISPLAY DEVICE, AND DISPLAY DEVICE AND ELECTRONIC APPLIANCE INCORPORATING THE SAME - An object is to realize downsizing and cost reduction of a display device by efficiently using a physical region of a memory in a control circuit of the display device. A structure of a video data storage portion of the control circuit is that provided with a video data storage portion for storing video data of an n-th frame (n is a natural number), a video data storage portion for storing video data of an (n+1)th frame, and a video data storage portion for sharing video data of the n-th frame and the (n+1)th frame among received video data. | 03-31-2011 |
20110261864 | SEMICONDUCTOR DEVICE - In a case where an ASK method is used for a communication method between a semiconductor device and a reader/writer, the amplitude of a radio signal is changed by data transmitted from the semiconductor device to the reader/writer when data is not transmitted from the reader/writer to the semiconductor device. Therefore, in some cases, the semiconductor device mistakes data transmitted from the semiconductor device itself for data transmitted from the reader/writer to the semiconductor device. The semiconductor device includes an antenna circuit, a transmission circuit, a reception circuit, and an arithmetic processing circuit. The antenna circuit transmits and receives a radio signal. The transmission circuit outputs to the reception circuit a signal showing whether or not the antenna circuit is transmitting the radio signal. | 10-27-2011 |
20110298975 | CONTROL CIRCUIT OF DISPLAY DEVICE, AND DISPLAY DEVICE, AND DISPLAY DEVICE AND ELECTRONIC APPLIANCE INCORPORATING THE SAME - An object is to realize downsizing and cost reduction of a display device by efficiently using a physical region of a memory in a control circuit of the display device. A structure of a video data storage portion of the control circuit is that provided with a video data storage portion for storing video data of an n-th frame (n is a natural number), a video data storage portion for storing video data of an (n+1)th frame, and a video data storage portion for sharing video data of the n-th frame and the (n+1)th frame among received video data. | 12-08-2011 |
20120081186 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - A semiconductor device includes an antenna circuit for receiving a wireless signal, a power supply circuit generating power by the wireless signal received by the antenna circuit, and a clock generation circuit to which power is supplied. The clock generation circuit includes a ring oscillator which self-oscillates and a frequency divider which adjusts frequency of an output signal of the ring oscillator in an appropriate range. A digital circuit portion is driven by a clock having high frequency accuracy, so that a malfunction such as an incorrect operation or no response is prevented. | 04-05-2012 |
20120132719 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with a power supply circuit having a function to generate a power supply voltage from a wireless signal and an A/D converter circuit having a function to detect the strength of the wireless signal by an A/D conversion of a voltage generated from the wireless signal. This enables to provide a semiconductor device which does not require replacement of batteries, has few limitations on its physical shape and mass, and has a function to detect a physical position. By formation of the semiconductor device with use of a thin film transistor formed over a plastic substrate, a lightweight semiconductor device, which has flexibility in physical shape and a function to detect a physical location, can be provided at low cost. | 05-31-2012 |
20120173915 | Clock Generation Circuit and Semiconductor Device Including the Same - Objects of the invention are to provide a clock generation circuit and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit. The frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value. | 07-05-2012 |