Arora, Bangalore
Ankur Arora, Bangalore IN
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20150331806 | MANAGING ASYMMETRIC MEMORY SYSTEM AS A CACHE DEVICE - Some implementations provide a method for managing data in a storage system that includes a persistent storage device and a non-volatile random access memory (NVRAM) cache device. The method includes: accessing a direct mapping between a logical address associated with data stored on the persistent storage device and a physical address on the NVRAM cache device; receiving, from a host computing device coupled to the storage system, a request to access a particular unit of data stored on the persistent storage device; using the direct mapping as a basis between the logical address associated with the data stored on the persistent storage device and the physical address on the NVRAM cache device to determine whether the particular unit of data being requested is present on the NVRAM cache device. | 11-19-2015 |
Manoj K. Arora, Bangalore IN
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20120047333 | EXTENDING A CACHE COHERENCY SNOOP BROADCAST PROTOCOL WITH DIRECTORY INFORMATION - In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed. | 02-23-2012 |
20120131282 | Providing A Directory Cache For Peripheral Devices - In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed. | 05-24-2012 |
20140115274 | EXTENDING A CACHE COHERENCY SNOOP BROADCAST PROTOCOL WITH DIRECTORY INFORMATION - In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed. | 04-24-2014 |
20140181394 | DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS - Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor. | 06-26-2014 |
20140359230 | PROTOCOL FOR CONFLICTING MEMORY TRANSACTIONS - Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions. | 12-04-2014 |
20150081977 | EXTENDING A CACHE COHERENCY SNOOP BROADCAST PROTOCOL WITH DIRECTORY INFORMATION - In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed. | 03-19-2015 |
Prashant Arora, Bangalore IN
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20150347646 | NUMERICAL APPROACH FOR COMPUTING FLUID FLOW VARIABLES FOR THREE-WAY FLOW COMPONENTS IN 1D FLUID FLOW NETWORKS - A numerical approach for computing fluid flow variables for three-way components in one-dimensional (1D) fluid flow networks is disclosed. In one embodiment, a first flow configuration type of a three-way flow component is determined using geometric properties and fluid flow characteristics of the three-way flow component. Further, a first flow ratio for the three-way flow component is computed using the first flow configuration type. Furthermore, fluid flow loss coefficients for the three-way flow component are obtained based on the geometric properties and the first flow ratio. Also, equivalent pipe loss coefficients for each pipe in the three-way flow component are computed from normalization of the obtained fluid flow loss coefficients. Moreover, the fluid flow variables are numerically solved for using the obtained equivalent pipe loss coefficients, the geometric properties and the fluid flow characteristics of the three-way flow component. | 12-03-2015 |
20160042096 | SYSTEM AND METHOD OF GENERATING AN AXIALLY STRUCTURED VOLUME MESH FOR SIMULATING DESIGN COMPONENTS - A system and method of generating an axially structured volume mesh for simulating a design component are disclosed. In one embodiment, the axially structured volume mesh having hexahedral cells on boundary layers of the design component and wedges and/or polyhedral cells along length of remaining part of the design component is generated. | 02-11-2016 |
Praveen Arora, Bangalore IN
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20100107151 | METHOD AND SYSTEM FOR IMPLEMENTING PERFORMANCE KITS - Described is an improved method, system, and computer program product for implementing performance kits. Test data for the performance kit is preloaded into an installation image that is distributed with a vendor's product. This avoids the need for the customer himself to have to perform the tasks of installing the test data at the customer site. | 04-29-2010 |
Rishi Arora, Bangalore IN
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20100114926 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING AUTOMATED WORKLISTS - A method, system, and computer program product for implementing automated worklists are provided. The method includes generating a worklist, which further includes retrieving a worklist template corresponding to the worklist and, via a first query, selecting a listing of members and attributes to be populated in the worklist, the attributes include a status indicator of an action item specified for each of the members of the worklist. The worklist generation also includes building a worklist member table with results of the first query and, via a second query, and using attributes of the worklist member table, identifying up-to-date values of one or more worklist member attributes, and outputting results of the second query to the worklist. The method also includes presenting the worklist to a corresponding assignee. For each of the members in the worklist, the status indicator is editable to update a status of the member. | 05-06-2010 |
Sampan Arora, Bangalore IN
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20090024876 | System and Method for Verification of Cache Snoop Logic and Coherency Between Instruction & Data Caches for Processor Design Verification and Validation - A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly. | 01-22-2009 |
20090024886 | System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation - A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address/granule “succeeds” only if the reservation for the granule still exists (conditional store). Since the reservation may be lost due to situations such as, for example, a processor (or another processor) executing a different lwarx or ldarx instruction (or other mechanism), which clears the first reservation and establishes a new reservation, the invention described herein builds test patterns in a manner that ensures, stwcx success and failure predictability. As a result, stwcx instructions are testable during test pattern execution. | 01-22-2009 |
20090024894 | SYSTEM AND METHOD FOR PREDICTING IWARX AND STWCX INSTRUCTIONS IN TEST PATTERN GENERATION AND SIMULATION FOR PROCESSOR DESIGN VERIFICATION/VALIDATION IN INTERRUPT MODE - During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store instruction is adapted to store the pseudo-random address in a predetermined memory location. The test pattern generator also builds an interrupt service routine that services an interrupt associated with the interrupt request; checks the predetermined memory location; determines that the pseudo-random address is located in the predetermined memory location; and executes a subsequent lwarx instruction using the pseudo-random address. | 01-22-2009 |
20090070629 | System and Method for Testing Multiple Processor Modes for Processor Design Verification and Validation - A system and method for generating a test case and a bit mask that allows a test case executor the ability to re-execute the test case multiple times using different machine state register bit sets. A test case generator creates a bit mask based upon identified invariant bits and semi-invariant bits. The test case generator includes compensation values corresponding to the semi-invariant bits into a test case, and provides the test case, along with the bit mask, to a test case executor. In turn, the test case executor dispatches the test case multiple times, each time with a different machine state register bit set, to a processor. Each of the machine state register bit sets places the processor in different modes. | 03-12-2009 |
20090070631 | System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation - A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor. | 03-12-2009 |
Sarit Arora, Bangalore IN
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20140067555 | METHOD AND SYSTEM FOR PROVIDING ONLINE ADVERTISEMENTS BASED ON USER DRIVEN DEVICE MOTION INPUTS - A method and system for providing online advertisements based on user driven device motion inputs. The method includes receiving one or more device motion inputs for a static advertisement from a user of an electronic device. The method also includes fetching data based on the one or more device motion inputs. The data includes at least one of acceleration data and multi-directional data. The method further includes correlating the data to one or more objects associated with the static advertisement. Further, the method includes creating an interactive advertisement based on correlation of the data to the one or more objects. Moreover, the method includes displaying the interactive advertisement to the user. The system includes an electronic device, communication interface, memory, and processor. | 03-06-2014 |
Satish Arora, Bangalore IN
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20100322415 | MULTILAYER ENCRYPTION OF A TRANSPORT STREAM DATA AND MODIFICATION OF A TRANSPORT HEADER - Several methods and a system of multilayer encryption of a transport stream data and modification of a transport header are disclosed. An exemplary embodiment provides a method of a multilayer encryption. The method includes further encrypting an initially encrypted transport stream data to generate a multilayer encrypted data using a processor and a memory. The method also includes determining a further encryption flag data. The encryption method modifies a transport header of the multilayer encrypted data. In addition, the encryption method includes the further encryption flag data in an adapted component of a modified transport header. | 12-23-2010 |
Silky Arora, Bangalore IN
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20110055797 | AUTOMATIC MONITOR GENERATION FROM QUANTITATIVE SCENARIO BASED REQUIREMENT SPECIFICATIONS - A method for validating a design model includes generating a requirement in the form of an event sequence chart with quantitative constraints and generating a monitor from the event sequence chart, wherein the monitor is configured to validate the design model with respect to the requirement. | 03-03-2011 |
Tejkumar Arora, Bangalore IN
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20160057077 | INTELLIGENT DATA CENTER SELECTION - In embodiments, a data center selection system can select a chosen data center (DC) for an order submitted to a cloud computing system using a preprocessing layer and a rules engine that incorporates action/algorithm-based selection using data center metrics to determine the chosen DC. In various embodiments, the data center selection system retrieves order information, objectives, rules, algorithms, and other data defined by an administrator. The data center selection system can then retrieve data center information aggregated from various data centers. Using order information received from an order management system, the data center selection system can utilizes the preprocessing layer, the rules engine, and the algorithm-based selection to select the chosen DC. The data center selection system can send an order request to the chosen DC in which to provision services for the order request. | 02-25-2016 |
Vikram J. Arora, Bangalore IN
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20080320552 | ARCHITECTURE AND SYSTEM FOR ENTERPRISE THREAT MANAGEMENT - Enterprise threat assessment and management provides both physical and logical security. Physical access control systems are configured to identify physical events in the physical domain, and logical access control systems are configured to identify logical events in the logical domain. Connectors establish uninterrupted coupling to the physical and logical access control systems. Event middleware is configured to selectively subscribe only to those events that correspond to defined policies. The policies define a correlation of the physical and logical events, actions are initiated depending upon the correlated physical and logical events defined by the policies. | 12-25-2008 |
20090216587 | MAPPING OF PHYSICAL AND LOGICAL COORDINATES OF USERS WITH THAT OF THE NETWORK ELEMENTS - Physical coordinates of a user and an asset are determined. A probability that the user and the asset are close to one another is determined based on the physical coordinates of the user and the asset. Permission for the user to access to the asset is decided based on the probability. Additionally or alternatively, logical coordinates of a user and an asset are determined. The logical coordinates of the user and the asset are compared, and permission for the user to access to the asset is decided based on the comparison. | 08-27-2009 |